Silicon on Sapphire Wafer (SoS) for Researchers

university wafer substrates

Silicon-on-Insulator (SOS) Wafers Technology Applications:

  • analog-to-digital converters
  • monolithic digital isolation buffers
  • SOS-CMOS image sensor arrays
  • patch-clamp amplifiers
  • energy harvesting devices
  • three-dimensional (3D) integration with no galvanic connections
  • charge pumps
  • temperature sensors

Get your quote today. Just send us your specs/qty!

Silicon on Sapphire (SOS) Specification

Below are just some of the SoS wafers that we can make.

Please provide us with your specs/quantity for an immediate quote.

See bottom for more SoS inventory.

Material: 99.996% high purity monocrystalline Al2O3
Orientation: R-Plane (1-102)
Off-cut Non Off-cut: +/- 0.5 degree
Diameter: 100 +/- 0.1mm
Thickness: 460 +/- 20 microns
Primary Flat: 32.5 +/- 2.5 mm; 45 +/- 1 degree. From C on R
Front Surface: Finish EPI ready polished Ra </= 0.3 nm
Bow: </= 20 microns
TTV: </= 15 microns
Warp: </= 20 microns
Flatness (TIR): </= 12 microns
Back Surface: finish as lapped (Ra=0.6 +/- 0.2 um)
Laser Marking: None
Packaging: Atmosphere Argon vacuum packed in class 100 clean room
Additional Notes:
Metallic Contamination: <5E10 atoms/cm^2 by VPD for Ca, Na, K, Cr, Zn, Fe, Cu and Ni
LPD: </=40 @ >/=0.2 microns
Edge Exclusion: 3 mm

EPI Layer:
Thickness of Silicon (100) EPI Layer center point: 600 +/- 60nm
Film Crystallinity & Surface Quality: in accordance with SEMI M4-1296
Resistivity: >/= 100 ohm-cm (Undoped)
Microparticulate density (for particles greater than 2 microns);< 2 per cm^-2


Silicon-on-Sapphire (SoS) Inventory

Please let us know if you can use or if you need something else.

Dia. Ori Si film Pol Res Thick
4'' R+/-0.5deg 0.6um+/-10% P/E >100 460 um
4'' R+/-0.5deg 0.6um+/-10% P/E <100 460 um
4'' R+/-0.5deg 0.75um+/-10% P/E >100 460 um
4'' R+/-0.5deg 0.80um+/-10% P/E >100 460 um
4'' R+/-0.5deg 0.85um+/-10% P/E >100 460 um
4'' R+/-0.5deg 3000nm+/-5% P/E >100 460 um
4'' R+/-0.5deg Dummy-grade P/E Dummy-grade 460 um
6'' R+/-0.2deg 100+/-10nm P/E >100 460 um
          460 um
4'' R+/-0.5deg 100+/-10nm P/P >100 460 um
4'' R+/-0.5deg 230+/-10nm P/P >100 460 um
4'' R+/-0.5deg 600nm+/-10% P/P >100 460 um
4'' R+/-0.5deg 1500nm+/-10% P/P <100 460 um
4'' R+/-0.5deg 3000nm+/-5% P/P >100 460 um

How to Fabricate Silicon on Sapphire Wafers for Silicon on Silicon Applications

In the 1960s, the concept of using monocrystalline Si on sapphire substrates was first proposed by North American Aviation, now known as Boeing. The technology involved a high-temperature deposit of silicon onto a sapphire wafer. One major advantage of this type of semiconductor is its superior linearity and low parasitic capacitance. These properties are essential for electronic circuits. It also offers improved speed and lower power consumption.

The lack of supply has led to the development of non-standard methods for marking sapphire substrates. The asymmetrical corner shape of a single orientation flat, for example, lends a tactile and visual asymmetry to the finished product. In addition, the material's high thermal resistance and low power consumption make it ideal for many silicon on sapphire applications. For this reason, epiel has been developing innovative solutions for manufacturing silicon on a sapphire substrate.

In order to use SOS, high-purity sapphire crystals are usually used. The process is known to produce lattice disparities because sapphire is an excellent electrical insulator. As such, SOS is ideal for many types of electronics. However, SOS has encountered early challenges when it comes to commercial manufacture. The resulting crystal lattices can differ, limiting their use in electronics.