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Moore's law is not a natural law, but one made up to provide future expectation that the density of a microchip will double, on average, every two years. This decreases the chips speed while increasing its performce.
The cost of the chip is miniscule to the designing of the chip architecture. The smaller you go the harder it is to fabricate how the electrons flow and what connects to what.
It's often believed that Moore's Law will soon end. However this seems highly unlikely as engineers are working hard to extend the future of the law.
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Substrate Recommended for Mid-Infrared Transparency
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Stacking Gallium Nitride & Silicon Transistors On Silicon Wafers
How UniversityWafer Helps Medical Research?
We are very active in the medical research field. We provide the highest quality, lowest cost substrates for the following:
Graphene Based Sensors
Biosensors to Detect Proteins in Saliva
Borofloat (33) glass substrates coated with a thin film of chrome, gold and titanium to fabricate an IDE pattern used to develop an interdigitated electrode sensor platform targeting the Plasmodium falciparum Histidine Rich Protein 2 (PfHRP2) protein in saliva samples.
Polished silicon wafers were used to determine if cells cultured in a 3 Dimensional (3D) matrix have a softening behavior and to link it to cytoskeletal remodeling.
Micro-Droplets for Cell Encapsulation
Silicon Nitride Wafers Used in Nanopore Sensing Device for DNA Detection
Researchers have used a thin nitride membrane will seperate two buffers. One buffer will contain DNA. There will be a single pore in the membrane. When applying a bias across the pore, DNA will begin to translocate and we can detect them by the drop in current.
Silicon wafers will be used as the substrate upon which we can deposit silicon nitride. Ultimately, the silicon will be etched away, leaving only the nitride membrane.
Fabricating 4 inch 500nm Crystalline Gallium Phosphide (GaP) Film on ~500um Quartz
To grow monocrystalline GaP 500nm thick, you need to grow it on a substrate that is lattice matched to GaP. Both Quartz and Sapphire are far away from that.
By MOCVD, one can grow GaP on Silicon (Si) - Lattice constants are GaP: 0.54505nm, Si: 0.54310nm. The cost would be about $2,000 for 500nm of GaP on 2"Ø Si wafer.
If your objective is to grow GaP on an insulator then consider growing it on high resistivity Silicon with Ro > 20KOhmcm.
Another possibility is to grow Thermal Oxide (SiO2) on a Silicon wafer and then GaP on SiO2.
Thermal Oxide is close to being monocrystalline and so maintains the lattice spacing of Si, that is 0.54310. This is in contrast to Quartz which exhibits Lattice constants of 0.49137 and0.54050.
I dare not estimate the cost of GaP/SiO2/Si because I do not know of a facility that has actually achieved such Epi growth Theoretically it is possible and chances are that it can be done.
Likely I can get an MOCVD facility to take it on but only as a "best effort" research project.
Graphene-Based Device Research
As you probably know we grow graphene in our reactor via Chemical Vapour Deposition (CVD) method. We use a 18μm thick copper foil as catalyst and methane as a carbon source. We usually use a ferric chloride solution to etch the copper foil and we use a PMMA assisted WET transfer process to transfer the graphene film onto the final substrate.
Please, find attached the TDS for "Graphenea Monolayer Graphene film on various substrates" and the Raman spectra of one of our batches.
We also produce Graphene Oxides by chemical exfoliation of graphite stone. We use our patented modification of the Hummer's method.
Please request the spec sheets 253557.
Alumina Wafers for HDPCVD Cleaning Application
Research client asks: Do you have 4" single flat ceramic alumina wafers? I've got a HDPCVD cleaning application that I think needs alumina dummy wafers?
UniversityWafer, Inc. Quoted:
Roughness(Polished): Ra 0.02~0.05nm
Cut one flat: 32mm ±2.0mm
How Silicon Wafers are used to grow Nanotubes
Nano-systems technologies present the pathway to the future. This is due to the ability of such systems to address the inefficiencies evident in the currently existing technologies. Researchers are laboring towards addressing the challenge of power consumption required by electronic devices. There is a general requirement of powerful devices that use limited power. Currently, all the possibilities have been explored thus necessitating new technologies altogether. Another inefficiency that has to be addressed is the memory issue, where minute devices are needed that can hold more and more information compared to the existing devices. Other challenges are computing power and connectivity. To build nanotubes, we have to apply new and emerging technologies.
Carbon nanotubes (CNTs) are formed by rolling a sheet of graphene forming a nanocylinder that has a diameter of one, one and a half nanometers. The nanocylinders can then be combined in tens of thousands within a specified diameter. Given that they are really small, Carbon nanotube field-effect transistors (CNFET) can be made from them. The transistor does operate similarly to the silicon transistor. Silicon transistors can be converted to carbon nanotube field-effect transistors by replacing the silicon with carbon nanotubes.
The current technologies use two-dimensional chips. Given that data has to be accessed one bit at a time, the approach is considered to be relatively slow. Better results can be obtained by stacking chips together. Two-dimensional substrates are physically stacked together with two-dimensional chips. Through silicon vias (TSVs) glue the different two-dimensional chips and wafers to each other. The TSVs are characterized as to be large and sparsely arranged. In simple terms, monolithic three-dimensional integration is achieved when different layers are built over each other on the same stirring substrate. No form of bonding is needed while carrying out the process. Monolithic integration is advantageous as it allows one to use nanoscale interlayer vias (ILVs) that currently exist in metal wires in chips today to connect all the different vertical layers.
Fabricating a silicon transistor requires way too high temperatures of about 1100 degrees Celsius to 1200 degrees Celsius. With this, it is impractical to stack silicon layers on top of the existing layer as the layer’s underneath would melt before the next layers have been built. With the new technology on nanotechnology, carbon nanotubes can be made at temperatures below two hundred degrees Celsius. There also exists a variety of memories where one can select from i.e. RRAM, CBRAM, STTMRAM.
Silicon wafers are used as the main basic bottom layer since it is fully compatible with the existing processing and design infrastructure. Also, silicon involves much processing in its fabrication process. The next process involves building metal wires as often as needed. After about three layers, the fourth layer can be made of carbon nanotube transistors. The result is a computer that can do several things. We begin with establishing a layer of memory circuitry, then we build accelerators that aid in supporting the chips embedded computing. After having layers of metal wires, we can have a layer of Carbon nanotubes. This new technology results in increased functionality as they can accommodate the incorporation of sensors such as gas sensors to be embedded in the chip.
With today's need for embedded computing and machine learning, large chunks of information have to be captured from the outside world and interpreted for out good. Also, new ways have to be found in handling activities such as medical screening and testing procedures that necessitate nanotechnology. A study on nanotubes is key to the future.
Consumer Products that use Silicon Safers
Electronic products that are bought by the consumer for use at a personal level are broadly classified as electronic consumer products. These products have to be physically present and do possess an integration feature to the current technology allowing for interaction with the user in a simple way. Microwaves, television, electric iron box, cellphones, and audio systems are examples of such products. The products use microelectronics integrated with the recent technology to meet the expected functionality. Even though the products may appear simple by physical appearance, they are rather complex in their underlying system. Besides, these products do not provide a few clues about the product itself or its operation (Jasper van Kuijk, 2017). The components that make consumer products may be grouped into three classes i.e. the core product, the extended product, and lastly the symbiotic elements. The picture below illustrates the three categorization classes of a consumer product.
Semiconductor materials used in making electronic devices are made using silicon wafers. In appearance, the wafers are made to be extremely flat disk-shaped, and mirror surfaced. Wafers can be categorized as the flattest items in the world as they are free from miniature surface irregularities. Since the 1960s silicon has been a reliable raw material choice in the manufacture of semiconductors. To date, about ninety-five percent of the devices that are existing in the market are made out of silicon. The worldwide wafer market for the year 2019 was estimated to stand at $9.85 billion and is expected to grow by $3.79 billion by the year 2025 (Contello, 2020). Semiconductors have been the building block of the current modern technology.
The current trend today is that the desire for electronic devices that are comparatively smaller, improved functionality, and faster than the ones existing today. This thus necessitates that the devices should be able to hold a higher number of transistors to aid it support additional features such as wireless computing. Miniaturization has further been propelled by the need for more compact electronics by the market. The ever-changing technology is availing alternatives to silicon though for a few applications. Despite the advancements, silicon still dominates. Integrated circuits used to power computers, microwaves, refrigerators, meters, or phones among other devices essentially use silicon. Consumer products such as virtual reality kits, drones, and smartwatches are predicted to be some of the key products that will expand the market for silicon wafers (Contello, 2020).
Different regions are trying hard to dominate the respective markets despite the existing hurdles. The Asia Pacific region tops the list of the largest market. With support from the respective administrations, the silicon wafer market is expected to have an upward trend. With the advent of the 5G technology, silicon wafer production is expected to increase to meet the expected high demand for smartphones supporting the 5G network. The new technology in place provides an opportunity for the entry of new consumer products thus there is a need for the development and improvement of the silicon wafer production. Firms are now restructuring their operations and focusing on specialization on specific wafer size diameters to have a competitive edge over their counterparts (Contello, 2020).
To convert a silicon crystal ingot to a wafer with the required quality standards, various processes have to be done. First, the single-crystal ingot has to be divided to form thin disk-shaped wafers. Then the edges of the wafer are profiled. The third process involves lapping or grinding to flatten the wafer surface. Then a chemical process is used to eliminate the processing damage existing on the wafer while minimizing mechanical damage. Next, a rough polishing operation has to follow to achieve a mirror surface on the wafer surface. A fine polishing process follows the rough polishing one to get the final mirror surface. Lastly, cleaning process is done to flush out unwanted material from the surface of the wafer (Z.J. Pei a, 2001). The picture below provides a summary of the whole process.
The high integration densities plus the requirement for miniaturization in consumer electronics has resulted in the discovery of chip stacking concept in three dimensions. Specialized packages for the three-dimensional chips have been developed by suppliers in the semiconductor industry. The concept of chip stacking is mostly applicable in memory devices or volume applications desiring high packing densities (Niklaus, 2002).
Companies dealing with consumer products continue to make noticeable steps on to new technology as they constantly are engaged in research. A particular company is Motorola that admits that silicon substrate wafers do offer robustness, high speed, good optical capabilities plus being cheap. This will boost high-speed communication and reduce the cost of microprocessor systems inclusive of optoelectronics and the monolithic incorporation of electronics. Other consumer devices such as DVD players are among the products projected to improve with such important discoveries (Motorola, 2001). With these technologies, the company can make integrated semiconductor circuits or Opto devices on a given wafer.
Last year the Singapore-MIT alliance for research and technology made it public that they had successfully found out how to incorporate silicon III-V in their designs. The current challenge with 5G mobile devices is that their processors are silicon-based CMOS chips that do have low efficiency and generate excess heat. This makes the devices to overheat shutting down the device after a few minutes. Also, in the same year, On Semiconductors did make an agreement with Cree Inc where Cree is to produce silicon carbide wafers and supply it to On Semiconductors. The figure below shows a summary of how consumer electronic demand steadily rises each year.