An electrical engineer requested a quote for the following:
Do you have 4" Si wafers, heavily doped N-type, <100>, <0.005 ohm-cm, SSP, prime grade with 300nm dry oxide? Oxide layer must be of good quality for use as gate dielectric.
What is the cost for 25 pcs of following with 300nm dry oxide?
Item #UW40105 Qty 25
Wafer Spec
N/As [100] 4" 525um P/E 0.001-0.005 ohm-cm Prime Grade 1 Flat
Item #G303 Qty 275
Wafer Spec
n-type Si:As [100] 4" 525 P/E 0.001-0.005 ohm-cm SEMI Prime, 2Flats, Epak cst, TTV<5
Reference #94378 for specs and pricing.
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An assistant professor and PhD candidate requested the following:
Does University wafer sell any silicon wafers patterned with metal. Something like 500 nm of Au on a thermal oxide wafer for source and drain electrodes (and gate dielectric) of a thin film transistor?
Highly doped p-type si, with thermal oxide highly polished on one side.
Thats about it. Diameter could also change is there is another side that is cheaper.
Do you need any other information?
Reference #118517 for specs and pricing.
I'm looking for a variety of oxide thicknesses on very conductive c-Si pieces, to be used as gate/dielectric for thin film transistors. Can I buy one of each for a total of 5 or more wafers, or does it need to be a minimum of 5 identical wafers?
Is it possible to get wafers with oxides of different thicknesses between 200 & 700 nm? I'd like to weigh all my options before I submit my order. Also, are there any price breaks that I could take advantage of around 5 wafers?
Reference #125401 for specs and pricing.
A postodoctioral student requested a quote for the following:
Could you could quote 3" wafers (~500um-thick) with these characteristics:
n+ Si substrate with 150-200 nm SiO2 only on top side of wafer. Oxide has to be of good quality (no pinholes) to use a gate dielectric.
Other specs are not important. Only very low resistivity n+ Si
and good quality dielectric. I can buy 5-10 wafers depending on the price.
Reference #129512 for specs and pricing.
A research scientist requested a quote for the following:
It should also have 200 nm dry oxide of premium quality since we will use it as a gate dielectric.
Just a few questions before. The quality is important for us since we
will use it in electronic research. I would like to know who
manufactures the wafers and which process they use (CZ or float zone?).
Is there a quality policy? We got a problem before where we received wet
oxide instead of dry oxide and was not good enough for us. The oxide will be used as a gate dielectric so it must be prime quality.
Reference #133686 for specs and pricing.
An assistant professor requested the following quote:
Hi, can you please provide me quotation for purchasing 100nm SiO2 gate dielectric thermally grown on p-type Si substrates. Do you also have 100nm SiO2 gate dielectric thermally grown on p- type Si substrates with 30 nm of Ta and 300nm of Au on the back side to allow gate probing through substrate. I am going to perpare Thin Film Transistor.
I am preparing N-type ZnO/SnO2 film and making effort to apply it in thin film transistors. I don’t need Si or SiO2 as my colleagues already ordered before from your company.
What I need is that a 100nm SiO2 film onto 30nm p-type Si substrates. Can you please kindly provide me a simple inventory for this wafer or do you have a similar product?
Reference #140815 for specs and pricing.
An assitant professor working at a Physics Department requested the follwoing quote:
We would like to have a layer of Al2O3 oxide (anything from ~30 nm to ~1 um) on top of Si's polished surface.
Also, please let us know if we send you an Si wafer patterned with Cr/Au/Cr (5nm/50nm/5nm), would you deposit Al2O3 for us?(Quote?)
The Al2O3 that you do by "sputtering", how does it compare to the one done by "atomic layer deposition (ALD)"? I know AL2O3 done by ALD gives really high insulating properties. We're looking to find an insulator which can bear ~2 MV/cm electric field without breakdown. The thickness doesn't really matter to us (as far as it is less than a few microns). We tried sputtered SiO2, but it leaked at 0.05 MV/cm. Do you know the k parameter (dielectric constant) of your sputtered AL2O3?
If you have any suggestions for other kinds of high-K gate dielectric materials, please let us know.
Reference #156825 for specs and pricing.
A Postdoctoral Scholar requested the following quote:
I am looking to use the wafers for two purposes, so perhaps you can advise if I chose the right ones from your stock list. I plan to use the undoped wafers to make sample plates for holding samples in a cryostat. We will use photolithography lift-off to make some metallic contacts, then dice up the wafer into smaller sample plates where samples can be mounted and wire bonded to, such that electric contact can be make in the socket on the cryostat. Perhaps ID num 3328 would work for this.
For the thermal oxide wafer we plan to mount exfoliated 2D samples and use the oxide as a gate dielectric. Perhaps ID num 1583 would work.
Please could you provide me a quote for: - 3x 100mm diameter, undoped (high resistivity), 500 or 525um thick, single side polished, silicon wafers - 2x 100mm diameter, doped (low resistivity), 500 or 525um thick, single side polished, silicon wafer with 300nm thermal oxidie SiO2.
Reference #260454 for specs and pricing.
In the past decade, metal-oxide-semiconductor field-effect transistors (MOSFET) have been scaled down to increasingly smaller sizes. However, this has been difficult to continue due to limiting factors such as gate leakage current.
Replacing silicon dioxide with a high-k dielectric can increase gate capacitance and drive current, thus raising device performance. Many different oxides have been proposed to replace silica, but most of them have challenges such as electrical quality, thermodynamic stability, kinetic stability and process compatibility.
The gate dielectric is a crucial component in MOSFET field-effect transistors, providing the electric insulation 
and capacitance necessary to perform electronic functions. Its performance is strongly influenced by its atomic structure and chemical composition. Metallic impurities contaminating the dielectric degrade its insulating and capacitive properties. Impurities also cause local reductions in the tunnel barrier and can induce traps that introduce a leakage path for charge carriers.
Maintaining the quality and reliability of gate oxide is one of the most challenging tasks in a semiconductor fab. In advanced CMOS technologies, the gate oxide thickness has shrunk to less than 30A thick — only about ten atomic layers — and its critical to maintain consistent quality across a twelve-inch wafer. With industry projections of further shrinkage of feature sizes, this trend will require the introduction of new gate dielectric materials that can meet demanding requirements.
Aluminum nitride (AlN) is a promising candidate for this purpose, with a lattice mismatch to SiC of only 1%, and nearly the same thermal expansion as silicon dioxide. In addition, it has a wider band gap energy than SiO2.
Another potential gate dielectric material is exfoliated h-BN, which offers a much higher breakdown voltage than traditional SiO2, and a bandgap close to that of the semiconductor. In the first demonstration of 2D materials-based n-channel organic field-effect transistors, exfoliated h-BN was used together with graphene, MoS2, and WSe2 as the working materials for the gate stack electrodes. This allowed for the fabrication of high-performance, low-power Ge n-channel MOSFETs with minimized off-state current leakage and on-to-off switching ratio.
In most cases the substrate used for a gate dielectric is silicon. However, there are other materials that are often used, such as boron nitride (h-BN), tungsten oxide (WO3), hafnium dioxide (HfO2), titanium oxide (TiO2) and aluminum oxide (AlO). For 2D material component devices, exfoliated h-BN is the choice of gate dielectric due to its combination of low dielectric constant and unique band structure (Bisi et al., 2018).
In the case of a MOS-C device, as the gate voltage increases the dynamic carrier generation and recombination moves toward net carrier generation. The positive gate voltage also attracts minority carriers at the substrate-to-oxide/well-to-oxide interface forming an inversion layer. Once this inversion layer reaches a critical depth, further increase of the gate voltage does not result in additional depletion of the semiconductor.
For this reason it is very important that the substrate has high reliability properties, such as thermal stability, process uniformity and defect morphology/density, especially in the presence of the gate dielectric. To achieve this, the underlying CMOS processes must be robust in the face of polishing microdamage and chemical oxidation damage (COP) as well as extended area defects such as epitaxial stacking faults. In addition, the atomic layer deposition (ALD) technology typically used in the industry is highly sensitive to the chemical composition of the underlying silicon substrate and the growth conditions.
The dielectric constant (k) is a property of the material that determines how much electric charge it can hold. Air has a dielectric constant of 1 while silicon dioxide, used as the gate oxide in old-fashioned CMOS transistors, has a k of about 3.9. The dielectric constant of a material affects the capacitance of a capacitor, but also how much it resists electric current. A low dielectric constant allows electrons to pass through the material more easily, while a high dielectric constant blocks them and limits their mobility.
The ideal gate dielectric should have a high enough dielectric constant to allow adequate current flow and be compatible with the process technology. It should also have a good thermal interface with the substrate to minimize carrier polarization and trapping at the metal/dielectric interface. The dielectric should also have a sufficiently wide band gap to allow sufficient electron mobilities for practical applications.
Hexagonal boron nitride (h-BN) has been proposed as an alternative gate dielectric to silicon dioxide due to its higher dielectric constant (k = 6.5), higher breakdown voltage (8-10 MV/cm), and narrower bandgap (6.3 eV). However, h-BN is a layered material that must be mechanically exfoliated or chemically synthesized at high temperatures. The Front End Processing (FEP) group will continue to evaluate new dielectrics that can meet these requirements, both in terms of process integration and device behavior.
The energy region that is unoccupied by electrons is called the band gap. If the material’s Fermi energy lies within this region, it is a semiconductor; if it is outside, it is an insulator.
There are some exceptions to this rule. Some materials that are insulators at normal temperatures may have small gaps in certain conditions, which can allow the transition of electrons between states. This phenomenon is known as a quantum tunneling effect.
In semiconductors, the gate dielectric can have a significant impact on the performance of the device. For example, in high-temperature operation, the generation and recombination of charge carriers at the dielectric interface can degrade the device’s performance.
For this reason, it is important to choose a gate dielectric with an appropriate band gap for the particular substrate in use. The energy position of the valence and conduction bands at the substrate surface can also play a role in the choice of gate dielectric.
For example, for 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs), the atomic layer deposition process of aluminum oxide (Al2O3) has demonstrated to be an excellent gate dielectric. This is due to the low work function of Al2O3, which can be tuned for both depletion and enhancement mode, as well as the relatively high energy position of the SiC valence and conduction bands with respect to the Al2O3 band gap (Kamimura et al., 2014).
Historically, silicon dioxide (SiO2) was the material of choice for the gate dielectric in silicon-based devices because of its excellent insulating properties and the ease with which it can be thermally grown on a silicon wafer. However, as devices have been scaled down in size to improve performance, the thickness of the gate dielectric has been reduced to the point where SiO2 is no longer effective at preventing leakage currents. Consequently, high-k dielectric materials (like hafnium oxide) have been introduced to replace or augment SiO2 in advanced devices. "High-k" refers to the high dielectric constant of these materials, which allows them to achieve the same capacitive effect as a much thinner layer of SiO2 but with reduced leakage.
A tenured professor requested help with the following:
I am looking for SOI wafer for MBE growth and simultaneously allowing back gating. For this we need a top layer consisting of Si(111) that is as high ohmic as possible (>1000Ohm/cm). Since we want to grow tetradymites on it (Bi2Te3 f.e.) a low miscut is also very favourable for us. The thickness of the oxide layer is not that important, as long as it can be used as a gate dielectric. The size of the wafer is also not that important as we will be cutting it into smaller pieces anyway.
The diameter is not that important, 4" would be best. The thickness of the oxide should be around 300nm and the Si(111) on top around 70nm. For the quantity 10 would be a good start, so we can test the Wafers. If the quality and specs are good, we would then order alot more.
Reference #273661 for specs and pricing.
A graduate research assistant requested a quote for the following:
Hi, I am looking for OFET with the channel length of 1 um. I was wondering if you could provide with fabricate device for 1 um channel length with Substrate / Gate- Silicon (p-doped), Gate dielectric- 300 nm silicon dioxide, Source-Drain electrodes - Platinum / Titanium adhesion layer.
Reference #275213 for specs and pricing.
A postdoc requted a quote for the following.
We would like to get some heavily doped silicon wafers with thin oxide as the gate dielectric for field effect transistor fabrication based on some n-type organic semiconductors. Would you please recommend some products (dopant type, resistivity, grade, oxide thickness, etc.)?
The diameter is not crucial, 4 inch or 6 inch wafer could work. We are looking at 5 to 10 pieces to get started.
Reference #275415 for specs and pricing.