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Silicon Wafers Particle Counts

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Silicon Wafer Particle Count

Cleaning a semiconductor wafer involves removing tiny silicon particles from its surface. This data would be typical for many different substrates, including other wafers, glass, ceramics and metals. VLSI micro-circuits are manufactured and cut, this example shows the "cleaning" of silicon particles on the substrate. [Sources: 6, 8, 11]

This is the cleaning process used on silicon wafer cells, and there are many different types of wafers that can be used in the semiconductor industry. In the early stages, silicon wafer manufacturers produce untreated silicon wafers and sell them to chip manufacturers who process them into chips in factories. Before sending the substrate to the chip manufacturer, the bare wafer must have exhibited only a few defects during the manufacturing process. [Sources: 4, 10]

The size of semiconductor devices and functions is expected to decrease steadily to 25 nm for DRAM and flash memory devices by 2015. Demand for 300 mm silicon wafers is strong, but the 200 mm arena is also growing. The challenges associated with inspecting unpatterned wafers include the growing challenge of particle size and the high cost of the process, "said Dr. Yoon-Hui Wang, Senior Vice President and Chief Technology Officer at Intel. Together with the decrease in critical killer particle sizes, they are expected to decrease to 12.5 nm [1]. Separately, the US Department of Energy (DOE) says it is mandatory to use unstructured wafer inspections. [Sources: 7, 10]

When electrostatic charge is present, fewer particles are counted and removed from the surface, but particles over 1 micrometer are already difficult to remove. When held by hand, the speed at which the probe is scanned affects the particle count. [Sources: 9]

The Contamination Wafer Standard uses silica nano particles in an SSIS tool with a high power supply and can be deposited completely or selectively. Silica particles are used by the reaction of particle size, which allows them to be deposited on a typical deposited substrate. A photo mask glass substrate can also be deposited in the size of the standard substrate, but a silicon wafer is typical for depositing on such a substrate. Customers can also offer a range of other options for wafer manufacturing, including the use of a standard standard or a standard micro-scale for a single-layer substrate, as well as a standard scale. [Sources: 2, 3, 5]

Patterned wafers may vary in topography due to the presence of particles, which can disable the circuit on the wafer. [Sources: 0]

When these particle types are deposited on a primary silicon wafer and scanned with a wafer inspection tool, the particle count is similar. For SPOT deposits, which would typically be 1000 - 2500 particles in size, the particle numbers are between 5000 and 25000. Complete deposition of the wafer is also ensured by the number of particles on the wafer ranging from 5000 to 10000. [Sources: 3]

The particle size standards available for deposition include the MSP NanoSilica (tm) Size standards, which include the SIO Size Standard (SOS) and the LSP Size Standard (LPD) as well as the SPOT standard. The measurement technology manager can specify the desired particle number for each particle to be deposited - size. When the wafer is measured with a particle counter, the pit detects particles with light spot defects ("LPD"). The number of particles before the test is then subtracted from the number of particles counted - the particles are counted and there is a number of adders. [Sources: 1, 2, 3, 9]

The size of the peak is determined by the emission of a single refractive index particle per peak, and the number of particles in the peak increases with size. [Sources: 5]

Based on the above facts, it is necessary to reduce the COP of OISF-L and L-D on silicon wafers used in the manufacture of semiconductor circuits. Since COP cannot be detected by a particle counter, a wafer is preferable as a method for assessing surface defects. A silicon wafer consisting of defect-free regions can be obtained from regions that are not contained in the wafer, such as those that lie within the surface of a single refractive index particle (i.e. on these wafers, only COP exists that is within that size). For this reason, the 300 mm Witness wafer is recommended as it generally has a smaller number of backgrounds and size and offers much higher protection against surface defects than any other silicon type. [Sources: 1, 2]

Spot deposition wafers have 1 or more particles of this size deposited on the clean silicon wafer surface surrounding them. More importantly, silicon dioxide (SiO2) particles are much more expensive than silicon dioxide (OISF - L and L-D), which costs about ten times more per square centimeter than silicon diodes. Many of these tiny particles also mix in the above-mentioned chemical solution and are scattered along the edges and inner surfaces of the semiconductor wafer. [Sources: 3, 5, 8]

This is because tiny particles of a silicon oxide film that detach from the surface of the semiconductor wafer are attached to the surfaces of the bare silicon during the fifth working step already mentioned. By injecting vacuum between the wafers and their surface, silicon waves can be heat-treated quickly in the atmosphere, allowing them to nitride silicon under high-temperature heating conditions. [Sources: 1, 8]




[0]: http://www.freepatentsonline.com/5076692.html

[1]: https://www.google.ch/patents/US7632349

[2]: https://tsi.com/products/wafer-and-reticle-inspection-standards/wafer-inspection-standards/

[3]: https://www.appliedphysicsusa.com/product/particlewaferstandards/

[4]: https://www.modutek.com/wet-processing-applications/wafer-cleaning-process/

[5]: http://www.particlewaferstandards.com/

[6]: https://www.co2clean.com/examples

[7]: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC3349508/

[8]: https://www.google.com/patents/US6973934

[9]: https://cleanroomtechnology.com/technical/article_page/Top_technique_for_surface_inspection/52574

[10]: https://semiengineering.com/inspecting-unpatterned-wafers/

[11]: https://en.wikipedia.org/wiki/Wafer_(electronics)