Gold Coated Silicon Wafers for Research & Production

University Wafer Silicon Wafers and Semicondcutor Substrates Services
University Silicon Wafer for Production

What are Gold Coated Silicon Wafers Used For?

Silicon wafers with gold deposited onto the surface are used in soft lithography for micro and nanoscale patterning.

Applications include:

  • nanotechnology
  • biotechnology
  • AFM applications.

Gold Coated Silicon Wafers

Deposition Technique: Electron Beam
Deposition Rate: 1-2 Å/sec
Vapor Pressure: 10-6 Torr
Adhesion Layer: Cr (99.99%)

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Gold Coated Silicon Wafers for Research & Production

We have gold coated Si wafers and we can deposit gold onto most any substrate. A thin layer of titanium (Ti) is used as an adhesion layer so the gold easily bonds to the single crystal silicon wafer.

Please email the specs and quantity that you would like.

Research Client Asks:

I need some gold-coated Si wafers. Gold thickness between 50-200 nm either sputtered or evaporated would be fine. These will be diced so wafer size is not critical - please use the below as a guide but let me know what you have in stock and/or what gives the best area/$. Could you please send me prices for: 1 x 4" wafer 10 x 4" wafer 1 x 6" wafer Are you able to offer a wafer dicing service for these? If so, please let me know the cost for dicing into 10x10 mm squares.

I only care about one side having a well-adhered gold layer – this is for an electrochemical sensor application. In the past I have always used something like: Boron doped 10-100 Ohm-cm <100> SSP, usually with 200 or 300 nm of a thermal oxide. In this application I don’t think the oxide layer is actually necessary.

UniversityWafer, Inc.'s Response:

The following wafers will work:

Si Item #1432
100mm P/B <100> 1-10 ohm-cm 500um SSP Prime

Si Item #3495
150mm P/B <100> 1-30 ohm-cm 620-675um SSP Prime with 300nm of Thermal Oxide

Gold Coated Undoped Silicon for Spectroscopy

The following undoped silicon wafer was used to fabricate a highly reflective layer of evaporated gold onto the wafer's polished surface. It is used for for spectroscopy experiments.

Undoped Si Item #2018

50.8mm Undoped Undoped <100> >10000 280um DSP Prime

Fabricating Gold (Au) Nanoparticles Film On Silicon (Si) Wafer By Self-Assembly


Gold nanoparticles (AuNPs) distributed on solid substrates have attracted a lot of attention in recent years, especially in the field of nanotechnology. The number of gold nanoparticle ordered arrays (NAPs) and their applications has increased in recent years due to their potential use in a wide range of applications in electronics, medical devices and other fields of science and technology, as well as in medicine and medicine. [Sources: 2, 4]

This invention has the advantage of low cost and can offer a wide range of applications in electronics, medical devices and other fields of science and medicine. Not only that, it can be used as a potential material in the ser-reinforcing effect and preferably has a strong binding force, similar to that of gold nanowires. The gold nanograins are produced by using a gold nanoparticle film on a silicon wafer, a solid substrate. [Sources: 8]

As shown in Fig. 5, today's inventors have successfully demonstrated that their technology performs the selective self-assembly of the gold nanoparticles. They have also demonstrated the ability to functionalize the gold nanoparticles by using different types of ligands, polymers and biomolecules. This supramolecular approach is similar to that of Xu and his colleagues, who used gold nanograins in their film. [Sources: 0, 6, 9]

This dispersibility behaviour will give graphene oxide particles the ability to be incorporated into polymer matrices for thin film production. [Sources: 5]

A graphene oxide film can be reduced, like electrons, by graphene oxide layers. A thin layer is available on various substrates such as glass, quartz, PET and Si. SiO2 on the substrate wafer and facilitates the formation of monolayer nanoparticles by keeping them close to the surface. It has been proposed that graphene oxides can be applied naturally to a substrate such as silicon wafer, glass or quartz or PET-Si and be accessible to people involved in nuclear microscopy studies. [Sources: 5, 9]

The native oxides can be removed to produce controllable and repeatable oxidized silicon substrates. MPTMS functionalizes silicon wafers and functionalized silicon substrate and minimizes the need to replace CTAB-capped gold nanorodes with thiols. This promotes the ability to position removable silicone oxide - enriched silicon on its substrate. [Sources: 2, 10]

The removal of the native oxide layer from the BOE solution immediately before the deposition of sputtering leads to an ultra-thin infiltration threshold, i.e. a surface tension gradient of less than 0.5 mm / S. S., London. This environment induces a thin film of liquid that begins to climb the substrate surface due to the surface tensions and gradients that occur on the film surface. [Sources: 9, 10]

The following procedures were performed according to the literature and the contact angle of 89 degrees was determined when the silicon wafer was treated with MPTMS. This indicates the hydrophobic character of the substrate, probably due to imperfections in MP tMS sam. The use of a thin liquid film with a surface tension gradient of less than 0.5 mm was used to minimize the number of defects on the APTES monolayer that may appear as intrinsic wafer defects. [Sources: 1, 2]

The characterization of the MPTMS-grafted silicon wafer was performed by scanning electron microscopy under high vacuum conditions. The sample consisted of nanosquared hole templates produced by electron beam lithography by exposing a 20 nm HSQ resistor. These holes were filled with 8 - 9 nm gold nanoparticles, which were assembled using a spread-mediated and directed self-assembly technique. For comparison with the nanoparticle, a thin film of graphene oxide was used to functionalize the substrate, which was produced by means of a magnetron sputter reactor. To investigate the properties of GO thin films GO under near-infrared laser light, chemically and thermally reduced graphene oxides were produced using a simple vacuum filtration method and presented to GO. [Sources: 0, 2, 5, 9]

The self-assembly of GNRD is structured by solvent evaporation in combination with a silicone oxide-enriched substrate. The honeycomb structure - patterned thin layers of gold nanoparticles on the silicon wafer - was achieved by colloidal lithography on a solution surface and its structure was determined by electromagnetic resonance spectroscopy (EMS) under near-infrared laser light. [Sources: 2, 7]

Gold nanoparticles (AuNPs) of uniform size were produced using organic amines as size control reagents and reduction reagents. As shown in Fig. 3, a hexagonal lattice guided by a 9 nm gold nanoparticle was used as a substrate for self-assembly of GNRD on a silicon wafer. [Sources: 9]

The process has been optimized and no gold chipping has been observed during the deposit, and step B shows that the layers of the nanoparticle layer have climbed and spread on the substrate micromeniscus [10]. Based on our experiments, as shown in Fig. 3, the result of self-assembly of GNRD on a silicon wafer with a hexagonal lattice of 9 nm gold nanoparticles is a bonded gold pattern on an oxidised 100% silicone wafer. [Sources: 3, 9, 10]

 

 

Sources:

[0]: https://www.frontiersin.org/articles/10.3389/fchem.2016.00008/full

[1]: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7153467/

[2]: https://journals.plos.org/plosone/article?id=10.1371/journal.pone.0195859

[3]: https://nanoscalereslett.springeropen.com/articles/10.1186/1556-276X-6-167

[4]: https://www.tandfonline.com/doi/full/10.1080/17458080.2018.1520399

[5]: http://lescelebrites.fr/3m6sddepa/graphene-oxide-film.html

[6]: https://www.sciencedaily.com/releases/2014/06/140609140940.htm

[7]: http://macfruver.com/1n2ozp/crystalline-tint-reddit.html

[8]: https://www.google.com/patents/CN102978592A?cl=en

[9]: https://patents.google.com/patent/WO2017018946A1/en

[10]: https://www.spiedigitallibrary.org/journals/journal-of-micro-nanolithography-mems-and-moems/volume-16/issue-01/014502/Fabrication-of-ultrahigh-aspect-ratio-silicon-nanostructures-using-self-assembled/10.1117/1.JMM.16.1.014502.full