Silicon on Insulator (SOI) Wafer Thin & Thick Device Layers

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Silicon on Insulator (SOI) Wafers

We specialize in Small quantities orders!Diced Silicon on Insulator Wafers

We also sell diced pieces of expensive Soitec and Simox wafers. You need to increase your semiconductor device’s performance by decreasing electrical losses. SOI wafers is the solution. SOI reduces the power required and heat that’s generated, thus increasing the device’s efficiency and speed.  SOI insulation, or oxide layer, thickness depends on the application.  Thermal oxide from a few nanometers thick to many microns can be used in microelectronics as it reduces short-channel effects. Silicon on insulator wafers  operate at lower temperature to doping. Higher device yield can be had because of SOI’s higher density.
SOI applications include

  • Silicon Photonics
  • Microelectronic Devices
  • Radio Frequency (RF) Devices

Get your SOI Quote FAST!


Silicon-on-Insulator for fabricating Silicon Waveguides

Researchers have been using the following specs to fabricate the following SOI wafers as there is no additional absorbtion loss due to doping in integrated photonics work.

  • Silicon Waveguides
  • Grating Couplers
  • Integrated Photonic Components

SOI Item #3536
25mm X 25mm P/B <100> 10-20 ohm-cm 725um SSP Prime

Other wafer diameters and dimensions are also available

UniversityWafer, Inc's silicon-on-insulator (SOI) wafers , can be used the following electronics applications:

  • ultra-low power signal processing
  • wireless connectivity
  • power, image sensors and silicon photonics applications
  • radio-frequency silicon-on-insulator (RF-SOI) substrates
  • ultra-low power connectivity RF

UniversityWafer, Inc. can provide researchers with a wide range of engineered substrates including fast growing segments like automotive, AI-IoT (AIoT) and 5G.

Bonded Silicon-on-Insulator for Nanomaterials Research

Researchers have used the following SOI wafer item to research nanomaterials (applied physics) for quantum/photonic computation.

Si Item #3213
150mm P/B <100> 675um SSP
Device Layer: 2um Device Res 17-23 ohm-cm
Oxide: 0.5um
Handle Layer: 675um Res 4.8-7.2 ohm-cm

SOI Wafer for Silicon Waveguides

Research clients have used our Silicon-on-Insulator wafers for their silicon waveguide research.

SOI Item #3536
25mm X 25mm P/B <100> 10-20 ohm-cm 725um SSP Prime
SOI square, Device: 220nm, BOX: 3000nm Handle thick: 725+/-15um, TTV: <1um

Silicon-on-Insulator (SOI) Wafers for Microfluidic Device Research

We are designing a microfluidic device and would like to use one of your SOI wafers (Item# 3213). We are thinking of etching out the oxide layer between Si layers and push the Si layers for better sealing. It is crucial in our design to know about the surface roughness of the two Si layers in contact with the sandwiched oxide layer since it directly affects the leak quality. I appreciate it if you could let me know about your typical roughnesses of the Si surfaces touching the oxide (not top or bottom layers). Also, can we customize these surface roughness?

How Silicon-on-Insulator Wafers Benefit Electronic Circuit Design?

Silicon on insulator is a type of digital electronic circuit design that utilizes an electronic device's conductors to create a very small space between the two conducting sides of the device - usually one side is composed of a conductive material and the other is made of an insulating material. Silicon on insulator is used to create an indoor electric field that is needed in many low power electronic applications. An electrical field can be created by connecting a source of electrons with a source of ground or airborne ions. When the source of electrons is moved into a region of high humidity, the electronic field created creates a voltage across the insulator that is used to power an amplifier or demultiplexer. In some designs, multiple silicon on insulator layers can also be applied to increase the total voltage across the device.

Silicon on insulator is made by applying thin layers of silicon oxide to metallic or flexible substrates such as wafer, plastic, and plastic composites. Silicon on substrates can resist damage to the substrate as well as the flow of moisture, so the coating does not need to be thick as might be necessary for traditional IC device applications. Silicon on substrate can also offer more accurate measurements of resistivity, conductivity, and bandwidth. These types of electronic devices can be fabricated using inexpensive methods and yields of high cost materials. One benefit of applying silicon on a substrate is that the substrate serves as a miniature vacuum and can be used to control temperatures. The low cost of fabrication relative to other alternative methods of electronic manufacturing makes this method particularly suitable for small to mid-size electronic components.

The insulating layer in the substrate is a wafer-like layer that is applied to the top surface of the device. The wafer-like layer of silicon-on-insulator is referred to as the quartz substrate. The research team can use the atomic layer deposition method to apply the silicon onto the quartz substrate. Once the silicon has been deposited, the researchers must carefully heat the wafer-like layer through conventional infrared radiation so that the substrate will be bonded correctly and retain its electronic properties.

What is an SOI Silicon Wafer?

In semiconductor manufacturing, silicon on insulator(SOI) technique is the fabrication of silicon devices on a thin, flat silicon substrate, to eliminate parasitic capacitance in the device, thus enhancing performance. This is done with the help of mechanical and electronic principles to provide an effective method for controlling the transfer of energy across the device's interfaces, which improves device power distribution. One can visualize the SOI process as an electric field is applied across the interface of the device to change the permeability.

This method of silicon on insulator fabrication has many benefits. On one hand, the cost is very low as less amount of materials and labor is required for making such devices. On the other hand, the process ensures that the thickness of the silicon layer is adjusted to get better device performance with added protection from the environment.

These devices are fabricated with the help of several techniques including, roll lamination, electrochemical process, surface impregnated gas or dielectric lamination and buried oxide lamination. The most common method of using soiled silicon in layers is to use surface impregnated gas to apply the silicon directly onto the substrate. A number of advantages come with this method. First, the thickness of the silicon layer is adjusted to get better device performance and second, the devices produced with this method are durable and rugged.

Another method of making these devices is by using soitec machines like Smart Cut and Smart Touch. They make the wafer's surface smooth and flat. However, they introduce some amount of heat to the wafer during the cutting process. Since silicon has a relatively high melting point, the soitec machine's electricity is required to be turned off to allow the wafer to cool before applying the silicon onto the substrate.

With soi wafer bonding, electrical energy is used instead of electricity to cut the silicon into sheets. The advantage with soi wafers lies in its energy efficiency. The procedure uses only half of the energy that it takes for Smart Cut or other similar methods. This is because only a small area is worked with the use of soi wafers. In addition to this, there is also a decrease in heat generation because there is no direct contact with the substrate. The resulting product is much stronger than most of the other conventional laminates available in the market.

SMIC (Silicon Substrate Implantation Charge) is another technique commonly used for forming devices on substrates. A thin, flat or curved electrode is first deposited directly onto the desired location. The substrate is then heated in the microwave or pneumatic chamber to promote a chemical reaction between the two electrode materials. Once the desired thickness has been reached, the semiconductor material is simply rolled onto the subframe and a process called supercooling is done to remove the dead cells.

On the other hand, soi semiconductor devices insulator is not used to manufacture electronic devices. Instead, these devices are made using a different method. Silicon oxide is used instead of silicon to form the insulating layer. The oxide is deposited on the surface of the device. To ensure that the oxide is smooth and flat, several processes are employed. This includes gas tumbling, which ensures a uniform distribution of the silicon throughout the device.

Another alternative to the direct method of applying silicon-on-insulator is the use of silicon carbide substrates. These are made by applying pressure on a substrate and heating it until a solid is formed. The substrate is then etched using a diamond-tipped tool to form the silicon carbide layer. This method allows researchers to make as many substrates as they need for a particular project, depending on the complexity of the project.


Expensive Soitec SOI SOITEC SOI Wafers and Simox SOI wafers DICED into small and affordable pieces!

Bonded SOI Wafers made to order in small quantiles and short lead times.

We work with several SOI manufacturers to provide small quantities of SOI to you. Whole wafers and diced pieces available at a deep discount

For example we have a potential order for 50 of the following:

100mm P/B (100) 500um 10-20 ohm-cm Prime Grade
Device 340nm
Oxide 1,000nm

The manufacturer's minimum quantity is 50 wafers. But you only need say 1-3 wafers. We could potential buy 50 and sell you just a few at a very reasonable cost.

Other diameters such as 150mm is also possible. IF this interests you, please let us know. Or fill out the form below and let us know which specs you need!

Below are just some of our Thin Device Layer SOI Inventory

ID Diam Type Dopant Orien Res (Ohm-cm) Thick (um) Polish Grade Description

Device: 220 nanometers, BOX: 3000nm Handle thick: 725+/-15um, TTV: <1um

3536 25mm X 25mm P B <100> 10--20 725um SSP Prime  

Device 2.2um BOX, 27.5 micron Device. Handle Res: 1000-2000 ohm-cm, Device Res: 0.004-0.006 ohm-cm

3308 100mm P B <100> 1000-2000 483um SSP Prime  

Device Layer: 2um, Oxide: 0.5um, Handle Layer: 675um. Device Res 17-23 ohm-cm, Handle Res 4.8-7.2 ohm-cm

3213 150mm P B <100> 10--20 675um SSP Test  

Device Layer: 220nm, Oxide: 2um, MFR PN: SMB-6P675-2-0.22

3381 150mm P B <100> 10--20 675um SSP Prime  

Device thickness: 70nm, Oxide thick: 2000nm

2551 200mm P B <100> ~1-20 725um SSP Prime  

Device: 220nm, BOX: 3,000nm

3523 200mm P B <100> 10--20 725um SSP Prime  

SIMOX Silicon-on-Insulator SOI

We have the following thin device layer SOI available in small and large quantities. Please fill out the form for an immediate quote.

100mm SOI WAFERS

DEVICE TOP LAYER:
Diameter: 100±0.2mm
Type/Dopant: P/B
Orientation: (1-0-0)±0.5°
Thickness: 220±10nm
Resistivity: 8.5-11.5 ohm-cm
Finish: Frontside Polished

BURIED THERMAL OXIDE:
Thickness: 3μm±5%

HANDLE LAYER:
Diameter: 100±0.2mm
Type/Dopant: P/B
Orientation: (1-0-0)±0.5°
Thickness: 725±15um
Resistivity: ≥750 ohm-cm
Notch: Semi Standard
Back Finish: Etched + Oxide

Overall Wafer:
Edge exclusion: ≤5mm
TTV: ≤5μm, Warp: ≤50μm, Bow: ≤50μm

150mm SOI WAFERS

DEVICE TOP LAYER:
Diameter: 150±0.5mm
Type/Dopant: P/B
Orientation: (1-0-0)±0.5°
Thickness: 220±10nm
Resistivity: 8.5-11.5 ohm-cm
Finish: Frontside Polished

BURIED THERMAL OXIDE:
Thickness: 3μm±5%

HANDLE LAYER:
Diameter: 150±0.5mm
Type/Dopant: P/B
Orientation: (1-0-0)±0.5°
Thickness: 725±15um
Resistivity: ≥750 ohm-cm
Notch: Semi Standard
Back Finish: Etched + Oxide

Overall Wafer:
Edge exclusion: ≤5mm
TTV: ≤5μm, Warp: ≤50μm, Bow: ≤50μm

SOI Wafers to Fabricate 2D Devices

This promise has spurred large areas of manufacturing in their research, from steam separation to etching. The versatile and powerful tools for characterizing 2D materials have proven to be a valuable tool for their research in materials science and engineering, such as 3D printing and photonics. This allows these effects to be used for the development of sensors based on 2d materials and for a wide range of other applications. Scientists have used the following SOI wafer for their experiments.

Item # 2551:
200mm SOI Type: P Dopant: B
Orientation: <100>
Resistivity: 1-20O/cm
Thickness: 725+/-25um
Device / Oxide thickness nm
70 / 2000

Buy online or send us the specs you would like us to quote.

How Silicon-on-Insulator (SOI) Wafers Are Fabricated

There are several techniques to make SOI Wafersx.

    • Wafer Bonding, then Precision Grinding and Polishing.

    • SIMOX: Separation by implantation of oxygen.

    • Ion Split SOI : Implanation of hydrogen forming a weakened region within the silicon.

    • BESOI: Bond and Etchback SOI, employing a SiGe etchstop layer.

Silicon-on-Insulator (SOI) CMOS Technology

The silicon dioxide (SiO2) insulating layer insulates integrated circuits and transistors of bulk materials and offers a number of advantages. It provides protection for packaging and assembly, which is crucial for the reliability of the product at extreme temperatures. Many of them qualify as MIL-STD-883, the most stringent standard in the world of electronics, and shield the integrated circuit inside the housing from extreme MIL-STD-883 environments. The methods and materials used to ensure quality and reliability in these harsh environments offer great flexibility and flexibility in packaging, assembly and packaging assembly for integrated circuits, as well as packaging or assembly of products that are critical to reliability and product at extreme temperatures.

SOI Wafer Advantages

  • Low leakage current to wafer increases circuit operation to 225°C continuous and excursions to 300°C
  • Reduces the capacitance for much faster and lower power circuits
  • Substantially reduces noise with isolation from the bulk silicon for sensitive mixed signal circuits

The robust packaging materials and methods are also applied to multi-chip modules (MCM). The design of 20 chips is implemented in one package, and the robustness of the material and method means that designs of up to 10 chips can be realized in a single package.

The high level of integration is achieved by the gate array technology (HT2000), which can contain up to 290k gates (usable gates) each.

The technology also supports analog and mixed signal designs, and the reliability of SOI CMOS products is guaranteed by a formal phase gate process.

Data acquisition and component reliability at the specifications level, and adaptation to a new generation of low-cost, high-performance CMOS technology, can dramatically improve reliability, service life and intelligent completion. Over 2.5 million hours of operation have been completed in the past three years, with an average of 1.2 million hours of operation per year.

What SOI Wafers Are Used in Lab Research to Fabricate Silicon Nano Membrane Photodiode?

A photodiode (PD) is a semiconductor naphthalene semiconductor that functions as an electronic switch. Herein, a series of silicon (NWs) nanowires (Nws) are shown to display excellent photodiode performance both at room temperature and when exposed to visible light. These devices also exhibit tunability in the number of nanowires that can be contained within the same device, and so can be used as opto-transparent devices with photo-discharge tolerance up to -40% of the voltage. A PD device is an inexpensive way to build a solar panel, since solar energy conversion efficiency is directly proportional to the square of the area enclosed by the device, and for this reason many solar panels can fit neatly onto a single PD. The photodiode devices shown here are fabricated using a highly effective method called ionic vented deposition.

Researchers have used the following SOI wafers for their photodiode research:

200mm SOI
Device Layer: 55nm
Oxide: 145nm
1-10 ohm-cm 500um DSP