Silicon on Insulator (SOI) Wafer Thin & Thick Device Layers

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Silicon on Insulator Wafers

We specialize in Small quantities orders!Diced Silicon on Insulator Wafers

You need to increase your semiconductor device’s performance by decreasing electrical losses. SOI wafers is the solution. SOI reduces the power required and heat that’s generated, thus increasing the device’s efficiency and speed.  SOI insulation, or oxide layer, thickness depends on the application.  Thermal oxide from a few nanometers thick to many microns can be used in microelectronics as it reduces short-channel effects. Silicon on insulator wafers  operate at lower temperature to doping. Higher device yield can be had because of SOI’s higher density.
SOI applications include

  • Silicon Photonics
  • Microelectronic Devices
  • Radio Frequency (RF) Devices

 

Get your SOI Quote FAST!


Silicon-on-Insulator for fabricating Silicon Waveguides

Researchers have been using the following specs to fabricate the following SOI wafers as there is no additional absorbtion loss due to doping in integrated photonics work.

  • Silicon Waveguides
  • Grating Couplers
  • Integrated Photonic Components

SOI Item #3536
25mm X 25mm P/B <100> 10-20 ohm-cm 725um SSP Prime

Other wafer diameters and dimensions are also available

UniversityWafer, Inc's silicon-on-insulator (SOI) wafers , can be used the following electronics applications:

  • ultra-low power signal processing
  • wireless connectivity
  • power, image sensors and silicon photonics applications
  • radio-frequency silicon-on-insulator (RF-SOI) substrates
  • ultra-low power connectivity RF

UniversityWafer, Inc. can provide researchers with a wide range of engineered substrates including fast growing segments like automotive, AI-IoT (AIoT) and 5G.

Bonded Silicon-on-Insulator for Nanomaterials Research

Researchers have used the following SOI wafer item to research nanomaterials (applied physics) for quantum/photonic computation.

Si Item #3213
150mm P/B <100> 675um SSP
Device Layer: 2um Device Res 17-23 ohm-cm
Oxide: 0.5um
Handle Layer: 675um Res 4.8-7.2 ohm-cm

SOI Wafer for Silicon Waveguides

Research clients have used our Silicon-on-Insulator wafers for their silicon waveguide research.

SOI Item #3536
25mm X 25mm P/B <100> 10-20 ohm-cm 725um SSP Prime
SOI square, Device: 220nm, BOX: 3000nm Handle thick: 725+/-15um, TTV: <1um

Silicon-on-Insulator (SOI) Wafers for Microfluidic Device Research

We are designing a microfluidic device and would like to use one of your SOI wafers (Item# 3213). We are thinking of etching out the oxide layer between Si layers and push the Si layers for better sealing. It is crucial in our design to know about the surface roughness of the two Si layers in contact with the sandwiched oxide layer since it directly affects the leak quality. I appreciate it if you could let me know about your typical roughnesses of the Si surfaces touching the oxide (not top or bottom layers). Also, can we customize these surface roughness?

Expensive Soitec SOI SOITEC SOI Wafers and Simox SOI wafers DICED into small and affordable pieces!

Bonded SOI Wafers made to order in small quantiles and short lead times.

We work with several SOI manufacturers to provide small quantities of SOI to you. Whole wafers and diced pieces available at a deep discount

For example we have a potential order for 50 of the following:

100mm P/B (100) 500um 10-20 ohm-cm Prime Grade
Device 340nm
Oxide 1,000nm

The manufacturer's minimum quantity is 50 wafers. But you only need say 1-3 wafers. We could potential buy 50 and sell you just a few at a very reasonable cost.

Other diameters such as 150mm is also possible. IF this interests you, please let us know. Or fill out the form below and let us know which specs you need!

Below are just some of our Thin Device Layer SOI Inventory

ID Diam Type Dopant Orien Res (Ohm-cm) Thick (um) Polish Grade Description

Device: 220 nanometers, BOX: 3000nm Handle thick: 725+/-15um, TTV: <1um

3536 25mm X 25mm P B <100> 10--20 725um SSP Prime  

Device 2.2um BOX, 27.5 micron Device. Handle Res: 1000-2000 ohm-cm, Device Res: 0.004-0.006 ohm-cm

3308 100mm P B <100> 1000-2000 483um SSP Prime  

Device Layer: 2um, Oxide: 0.5um, Handle Layer: 675um. Device Res 17-23 ohm-cm, Handle Res 4.8-7.2 ohm-cm

3213 150mm P B <100> 10--20 675um SSP Test  

Device Layer: 220nm, Oxide: 2um, MFR PN: SMB-6P675-2-0.22

3381 150mm P B <100> 10--20 675um SSP Prime  

Device thickness: 70nm, Oxide thick: 2000nm

2551 200mm P B <100> ~1-20 725um SSP Prime  

Device: 220nm, BOX: 3,000nm

3523 200mm P B <100> 10--20 725um SSP Prime  

SIMOX Silicon-on-Insulator SOI

We have the following thin device layer SOI available in small and large quantities. Please fill out the form for an immediate quote.

100mm SOI WAFERS

DEVICE TOP LAYER:
Diameter: 100±0.2mm
Type/Dopant: P/B
Orientation: (1-0-0)±0.5°
Thickness: 220±10nm
Resistivity: 8.5-11.5 ohm-cm
Finish: Frontside Polished

BURIED THERMAL OXIDE:
Thickness: 3μm±5%

HANDLE LAYER:
Diameter: 100±0.2mm
Type/Dopant: P/B
Orientation: (1-0-0)±0.5°
Thickness: 725±15um
Resistivity: ≥750 ohm-cm
Notch: Semi Standard
Back Finish: Etched + Oxide

Overall Wafer:
Edge exclusion: ≤5mm
TTV: ≤5μm, Warp: ≤50μm, Bow: ≤50μm

150mm SOI WAFERS

DEVICE TOP LAYER:
Diameter: 150±0.5mm
Type/Dopant: P/B
Orientation: (1-0-0)±0.5°
Thickness: 220±10nm
Resistivity: 8.5-11.5 ohm-cm
Finish: Frontside Polished

BURIED THERMAL OXIDE:
Thickness: 3μm±5%

HANDLE LAYER:
Diameter: 150±0.5mm
Type/Dopant: P/B
Orientation: (1-0-0)±0.5°
Thickness: 725±15um
Resistivity: ≥750 ohm-cm
Notch: Semi Standard
Back Finish: Etched + Oxide

Overall Wafer:
Edge exclusion: ≤5mm
TTV: ≤5μm, Warp: ≤50μm, Bow: ≤50μm

SOI Wafers to Fabricate 2D Devices

This promise has spurred large areas of manufacturing in their research, from steam separation to etching. The versatile and powerful tools for characterizing 2D materials have proven to be a valuable tool for their research in materials science and engineering, such as 3D printing and photonics. This allows these effects to be used for the development of sensors based on 2d materials and for a wide range of other applications. Scientists have used the following SOI wafer for their experiments.

Item # 2551:
200mm SOI Type: P Dopant: B
Orientation: <100>
Resistivity: 1-20O/cm
Thickness: 725+/-25um
Device / Oxide thickness nm
70 / 2000

Buy online or send us the specs you would like us to quote.

How Silicon-on-Insulator (SOI) Wafers Are Fabricated

There are several techniques to make SOI Wafersx.

    • Wafer Bonding, then Precision Grinding and Polishing.

    • SIMOX: Separation by implantation of oxygen.

    • Ion Split SOI : Implanation of hydrogen forming a weakened region within the silicon.

    • BESOI: Bond and Etchback SOI, employing a SiGe etchstop layer.

Silicon-on-Insulator (SOI) CMOS Technology

The silicon dioxide (SiO2) insulating layer insulates integrated circuits and transistors of bulk materials and offers a number of advantages. It provides protection for packaging and assembly, which is crucial for the reliability of the product at extreme temperatures. Many of them qualify as MIL-STD-883, the most stringent standard in the world of electronics, and shield the integrated circuit inside the housing from extreme MIL-STD-883 environments. The methods and materials used to ensure quality and reliability in these harsh environments offer great flexibility and flexibility in packaging, assembly and packaging assembly for integrated circuits, as well as packaging or assembly of products that are critical to reliability and product at extreme temperatures.

SOI Wafer Advantages

  • Low leakage current to wafer increases circuit operation to 225°C continuous and excursions to 300°C
  • Reduces the capacitance for much faster and lower power circuits
  • Substantially reduces noise with isolation from the bulk silicon for sensitive mixed signal circuits

The robust packaging materials and methods are also applied to multi-chip modules (MCM). The design of 20 chips is implemented in one package, and the robustness of the material and method means that designs of up to 10 chips can be realized in a single package.

The high level of integration is achieved by the gate array technology (HT2000), which can contain up to 290k gates (usable gates) each.

The technology also supports analog and mixed signal designs, and the reliability of SOI CMOS products is guaranteed by a formal phase gate process.

Data acquisition and component reliability at the specifications level, and adaptation to a new generation of low-cost, high-performance CMOS technology, can dramatically improve reliability, service life and intelligent completion. Over 2.5 million hours of operation have been completed in the past three years, with an average of 1.2 million hours of operation per year.