Silicon Wafer Roughness (RMS)

university wafer substrates

Low Roughness (RMS) Silicon Wafers for Template Stripping

A university researcher requested a quote for the following:

I am looking to purchase some flat (low RMS) silicon wafers for template stripping. The latter is a process whereby you deposit a thin gold film (100-200 nm) onto the surface, then glue a glass support onto the deposited gold, whereby the glass-glue-gold substrate ensemble can be removed from the wafer. The gold surface used for subsequent experiments is the flat, clean one originally in contact with the silicon/SiO2 native oxide (the template), and so this is why I am interested in using the flattest Si surfaces (to generate as flat a Au surface as possible - for subsequent preparation of self-assembled monolayers of alkanethiols).

Ideally, we would purchase 4 small wafers (approx. 2" diameter), and 2 larger ones (approx. 4" diameter) for initial testing.

Please reference #212354 for specs and pricing! Or Buy Online!

We polish silicon wafers to create a smooth surface to generate higher yields when making semiconductor devices. Polishing turns otherwise dull rough surface to one that is very flat with mirror like quality and is free of particles.

The majority of our wafers are polished using Chemical Mechanical Polishing (CMP).

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Ultra-Smooth Silicon Polish to Fabricate Nano-Structures

A Phd professor requested the following quote:

I am looking for Si wafers with ultra-smooth surfaces (rms roughness of <1nm). I would like to ask you if your manufacturer provides such wafers, and if so, I will appreciate your time and help if you can send me the quote(s) for the sought-after wafers. Need wafers with smoother surfaces (a few up to a couple of tens of angstroms).

Reference # 229535  for specs and pricing.

Best Silicon Wafer Surface Roughness

An engineering graduate student requested the following quote:

I am looking for the wafers with the following specs (similar to #763). Silicon, diameter of 50.8 mm, n-type (P) or p-type (B), resistivity: 1-10 Ohm-cm, 275 um; Qty: 25; Orientation: <100>; single side polished
I wonder if you have similar wafers but with better surface roughness (e.g., Rq <0.2 nm). What's the best surface roughness (Ra, or Rq) of the polished silicon wafer can you achieve?


The Si wafer surface roughness is guaranteed by repetition of the Chemical-Mechanical-Planarization (CMP) polishing process, not by any measurement, which would be destructive. For the polished side of the wafers the normal roughness value is <0.5nm.

The CofC doesn't mention any surface roughness measurements data as the roughness is guaranteed by repetition of the chemical-mechanical-planarization (CMP) polishing process.

Reference # 290012 for specs and pricing.

What is Silicon Wafer Roughness?

The surface roughness of a silicon wafer is an electrical property that degrades over time due to the interaction between silicon and other materials on the surface of the wafer. [Sources: 3]

High-surface silicon wafers are often used as substrate materials in the micromachinery and microelectronics sectors, but their round time is long and costly [2]. To meet the high demand for high-quality silicon wafer substrates for semiconductors, a study requires sintering of at least 4 inches in size. The Ra removal rate (MRR) is used to assess the shrewdness and is usually chosen as an evaluation indicator. To obtain an accurate measurement of the surface roughness of a 4-inch sintered silicon wafer, it must be lapped at a surface temperature of about 1,000 degrees Celsius. [Sources: 0, 1]

The figure shows that the surface roughness of the diameter of a silicon wafer decreases uniformly, but only in the middle somewhat slower than in other diameters. The rougher the surface of the DEPP polishing, the larger the size and the faster the polishing process will decrease. [Sources: 1]

The thickness of the column-shaped silicon wafer is higher when the internal stress from the nickel stress layer is low, which means that the induced stress is higher than with compressive loading. However, as nickel thickness increases and the tension between the nickel layers can be controlled depending on the layer thickness, it is expected that the stress caused by the nickel layer due to the presence of nickel in the silicon layer will be lower than the actual load. The voltage of a silicon wafer shifts from 69 - 28 degrees to a 2nths of 68 - 88 degrees at the main peak of its wafers, suggesting that there is a significant difference between surface roughness and predicted nickel - induced stresses. However, with increasing thickness, the induced voltage in silicon wafers decreases, leading to increased thickness in calcified silicon wafers. [Sources: 6]

A new equation has been created to predict the thickness of a flaking silicon wafer. If the initial crack can be calculated from the stress caused by the electrodeposition layer, the thickening of the silicone splitter can also be predicted. The new equations achieve the same result for the predicted thickness of flaking silicon wafers as for compressed loads. [Sources: 6]

Figure 10b shows the stress caused by the residual stress on the nickel layer and the thickness of the silicon chip. Figure 10 shows a simulation of an electrodeposition layer with a voltage 1,000 times higher than that of a compressed nickel charge. [Sources: 6]

Figure 5a shows the thickness of the flaking silicon wafer as a function of the nickel thickness and the residual stress of the nickel layer at a voltage 1,000 times higher than that of a nickel charge. [Sources: 6]

A 3D microscope image of a silicon wafer with a nickel layer at a voltage 1000 times higher than that of the nickel charge. Figure 5b shows the thickness and residual stress of the silicon and nickel layers with the same stress. [Sources: 4, 6]

The surface roughness of a silicon wafer can be evaluated by assessing both small and large regions. SIMS) the thickness and residual stress of the silicon and nickel layers with a annealing time of 1 h at 1000 degrees Celsius. The results show that the thickness of the silicon on the wafers is inversely proportional to the voltage, which means that the induced voltage on silicon wafers increases with decreasing internal voltage in the nickel layer. [Sources: 3, 6]

The second rough polishing step removes 100% of the silicon and further reduces the low-frequency surface roughness. Compared to conventional CMP, DEPP MRR increased by 17.6%, with the nickel stress layer removed, resulting in a silicon wafer with a rough surface of less than 10 nm. This is significantly lower than the typical rough surfaces of the traditional "CMP," which is used to polish silicon wafers. [Sources: 1, 2, 6]

The measured values of R and S are 1.5% and 2.1% of the surface roughness of the silicon wafer, respectively, as the comparison of the component characteristics shows. The measured values of e and e are 1: 45 and 1: 35 respectively; both are significantly lower than the typical rough surface of conventional CMP. A solar cell using a silicone wafer with fission formation is closer to -1: 35, which is almost + 1 compared to solar cells that use silicon wafers in abundance. [Sources: 6]

The column-shaped silicon wafer in Figure 6 is approximately 50 mm thick, and the deviation from the silicon wafer thickness remains below 2 mm [4]. Compared to the spectrum of a pure silicon wafer, the split silicon wafers show no apparent shift in the PL spectrum, suggesting that the band structure in the spalled silicon wafer remains unchanged by splitting. [Sources: 6]

This creates a surface roughness gradient that produces a polished silicon wafer excimer laser. The more abrasives involved in the removal of material, the higher the MRR and the greater the amount of material that must be abrasive. [Sources: 1, 5]