Zinc Oxide on Silicon

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Zinc Oxide on Silicon

The following wafers work

Thermal oxide Layer

  • Research Grade , about 80 % useful  area
  • SiO2 layer on 4" Silicon wafer
  • Dry Oxide layer thickness: 100 nm   ( 2000A)  +/-10%
  • Growth method - Dry oxidizing at 1000oC

  • Refractive index - 1.455

  • Note:  customized oxide layer available upon request from 50 nm - 1000 nm

Silicon Wafer Specifications:

  • Conductive type:          P-ype/ B-dped 
  • Resistivity:                <0.001- 0.005 ohm.cm
  • Size:                         4" +/- 0.5 mm x 0.5 mm
  • Orientation:                (100) +/- 1o
  • Polish:                        one side polished
  • Surface roughness:      < 5A

Researcher:

"I see that you have p-type silicon wafers that have 300nm of thermal oxide. I have a few questions about that. First I want to make sure that the thermal oxide is in fact SiO2. Is this correct? Also, does this type of wafer come in square shapes? I was hoping to print ZnO materials on this type of wafer in a square pattern. It would be much easier for me to work on a 10 mm by 10 mm wafer rather than a round one. Please let me know if you provide that.

Should we use Wet or Dry Oxide?"

UniversityWafer, Inc. Reply:

Definitely Dry Oxide.  We have a process for gate dielectrics.  It is used for other applications, but gate oxide is the primary purpose.  It starts with Dry Chlorinated Oxide and adds a post-oxidation anneal in forming gas.

Dry oxide grows much slower than Wet oxide.  This makes it much denser and a better dielectric.  The addition of chlorine is to tie up mobile ions in the silicon crystal lattice, especially sodium.  It ties them up chemically so that they cannot react with any part of the device or form a leakage pathway.  The reason for the anneal in forming gas is to clean up hanging material at the oxide/silicon junction.  There are always unfinished silicon chains at the interfaces that can provide a start for a pathway for current.  This anneal effectively heals the silicon surface to reduce or eliminate them.

Every part of this process is designed to prevent the formation of a pathway that stray current can use to reach the device.  This is ideal for gate oxides.  If your client wants to reduce the cost we can do it without the anneal and it will still be a large improvement over wet thermal oxide.

One thing to note is that we cannot process square substrates.  Very little semiconductor fabrication equipment can accommodate square substrates.  I think your client will find this to be true of other foundries.

So we would have to use regular diameters and then dice.