Substrates to Grow Silicon Dioxide

I was wondering if you happen to have some 4inch, or 8 inch wafers with 40um thick silicon dioxide on both sides -- the wafers can be single of double side polished and intrinsic (standard resistivity is ok, but high resistivity would be idea. Also would it be possible to obtain wafers with an even thicker oxide? The adhesion of the oxide to Si is very important. We need the 40um so i will have to pass on the 10um. Out of curiosity if I were to provide wafers with a patterned Si surface would you be able to oxidize them with the goal of growing 15um of wet oxide? Below are methods with patterned Si fins (depending on width and pitch) should in theory create really thick oxides; although an lpcvd dep step might be required:

Fabrication of thick silicon dioxide sacrificial and isolation blocks in a silicon substrate

Reference # 211190 for specs and pricing.

Silicon Dioxide to Fabricate Microfluidic Patterns

A chemistry engineer requested the following quote:

Need Four inch, single side polished, silicon test wafers; N <100> any resistivity; any thickness; any type/dopant; any back surface; any flats.  Initially I need 25 wafers with the following specifications: Four inch single side polished silicon test wafers; N<100> any res; any thickness; any type/dopant; any back surface; any flats

Actually I needed a detailed discussion, but now I will try to write it down. Briefly this is our microfluidic device fabrication procedure for which I need the silicon wafers: to get the desired microfluidic patterns we first thermally grow the silicon dioxide (>500 nm) on the silicon wafers > then do the HF etching to remove unwanted silicon dioxide from photolithographically processed wafers > then dice the wafers to get chips > and finally etch the bare silicon chips with silicon dioxide patterns at 70 degree C for 40 minutes using 40 % potassium hydroxide to remove the specific amount of silicon.

We need silicon wafers very frequently and had worked with another company before for many years. But recently we had the following few problems with their wafers, and that's why we are now planning to switch the vendor:

1. First problem was cutting those wafers using the pen type diamond cutter. Usually the pen shape cutter has worked well in the past, but last few times it did not. We thought the problem could be because the wafers were either very thick or not the specified <100> orientation, so we had to use the cleanroom dicing saw to cut through the wafers and get individual chips.

2. Second problem was with the etch rate. Following the above mentioned etching procedure usually we get (and need) >30 um feature height after etching. However with the last few batches the etch rate was terribly slow, and we had got barely < 5 um feature height even with the overnight etching. Considering the poor etch rate it seemed like the wafer orientation might be <111> but not the <100> that was mentioned in the order.

Now we believe the following specifications: four inch single side polished silicon test wafers; N<100> any res; any thickness; any type/dopant; any back surface; any flats should work for us (and has worked in the past). So considering the above discussion if you could confirm that the unknown problem should be solved with the wafers from your company then I would be ready to place the initial order of 25 wafers.