Substrates to Grow Silicon Dioxide

university wafer substrates

Silicon Dioxide to Fabricate FET Devices

A Nanobiology researcher requested the following quote:

We are looking for some high quality silicon wafers with a highly doped conducting silicon passivated by a uniform silicon dioxide layer. We want to use these for fabricating  Field Effect Transistor (FET) devices and conducting silicon is required to apply gate voltage.

May you please direct us to suitable products that you may have for this application.

I am looking for:

  • N-doped silicon, preferably 3" wafers, <100> with a resistivity less than 0.005 Ohm cm. I could not find any arsenic doped wafers on your website, which probably have lower resistivity than those of antimony- or phosphorus-doped wafers. I will also need a 300 nm SiO2 layer on one side of the flake (wafer).
  • Please also let me know the lowest price wafers with the requirement of <100> orientation and 300 nm SiO2 (either one or both side). Doped or undoped will not matter in this case.
  • Depending on the price and availability, I will be looking for buying 10-100 wafers of each.

Reference #225361 for specs and pricing.

Get Your Quote FAST! Or, Buy Online and Start Researching Today!


Silicon Dioxide (SiO2) Coated Substrates to Fabricate Graphene Based Biosensors

A university research associate used our substrates for the following project:

We are using the silicon and silicon dioxide wafers to fabricate graphene based biosensor for medical research purposes.

Reference #702781 for specs and pricing.

Silicon Dioxide Substrates for Atomic Force Micrscopy Research

A research scientist requested a quote for the following:

 I am interested in purchasing several substrates for a conductive AFMstudy. I need materials with a known dielectric constant in a range of ~2.5 to 11. I currently have a silicon/ thermal silicon dioxide substrate. I am interested in a pure silicon substrate, my main concern being that the dielectric constant is known relatively well, and a similar Si3N4 substrate with a known dielectric constant. I was also wondering if you have any porous silicon oxide, which has a very low dielectric constant. I am using these in a standard in-air AFM, so sample geometry is not that crucial. Ideally I would like something along the lines of a 1x1 cm square. Is this something that you could help me with?

UniversityWafer, Inc. Answered:

Per data the Dielectric Constant of Si at 300 K is ~11.9 

Reference #262707 for specs and pricing.

SiO2 Wafers to Deposit Polymer Fibers

A PhD Candidate in Materials Science requested the following quote:

I'm looking to buy 100 pieces (10mmx10m) of silicon dioxide wafers ( about 1micron oxide thickness). I’m using these chips as insulating substrates to deposit polymer fibers, so I don’t have any special requirements. 

Reference #258005 for specs and pricing.

Growing Silicon Dioxide Using Dry Chlorinated Theram Oxidation Service

A doctoral candidate requested the following quote:

I hope this finds you well. We would to request a quote for the deposition of 50 nm of silicon dioxide using dry chloronated thermal oxidation. The deposition would be performed by wafers supplied from our lab. But we have a few questions: 1. How many wafers can you have in a single lot run? 2. Is it possible to provide the oxidation at lower temperature (e.g. 800°C)? 3. What is the expected silicon dioxide thickness tolerance? +- 5% or +- 10%? 4. What is the expected lead time after the receipt of payment and wafers? 5. Do you perform RCA1 and RCA2 cleans prior to the oxidation service?

But due to an issue with our oxidation furnace, we are looking to obtain a quotation for thermal oxidation service on our wafers as mentioned in the University Wafer website.

We are looking for dry chloronated thermal oxide of 50 nm on our wafers. Looking forward to hearing from you. 

Reference #272655 for specs and pricing.


New Technique to Grow Thick Silicon Dioxide

Scientists have new silicon micromachining method to fabricate deep silicon dioxide blocks at selected locations in a silicon substrate surface. The method uses the following processes:

  • Deep-Reactive-Ion Etching (DRIE)
  • Thermal Oxidation
  • Deposition of silicon dioxide and optional planarization

Defined silicon dioxide blocks integratate silicon surface and bulk micromachining and thick large-area isolation regions for Integrated Circuits (ICs). The performance enhancement that this approach enables is exemplified in the fabrication of an on-chip tunable capacitor and a monolithic transformer on 20-μm-deep silicon dioxide blocks.

Thick Silicon Dioxide

A nanofabrication researcher requested a quote on the following:

I was wondering if you happen to have some 4inch, or 8 inch wafers with 40um thick silicon dioxide on both sides -- the wafers can be single of double side polished and intrinsic (standard resistivity is ok, but high resistivity would be idea. Also would it be possible to obtain wafers with an even thicker oxide? The adhesion of the oxide to Si is very important. We need the 40um so i will have to pass on the 10um. Out of curiosity if I were to provide wafers with a patterned Si surface would you be able to oxidize them with the goal of growing 15um of wet oxide? Below are methods with patterned Si fins (depending on width and pitch) should in theory create really thick oxides; although an lpcvd dep step might be required:

Fabrication of thick silicon dioxide sacrificial and isolation blocks in a silicon substrate

Reference # 211190 for specs and pricing.

Silicon Dioxide to Fabricate Microfluidic Patterns

A chemistry engineer requested the following quote:

Need Four inch, single side polished, silicon test wafers; N <100> any resistivity; any thickness; any type/dopant; any back surface; any flats.  Initially I need 25 wafers with the following specifications: Four inch single side polished silicon test wafers; N<100> any res; any thickness; any type/dopant; any back surface; any flats

Actually I needed a detailed discussion, but now I will try to write it down. Briefly this is our microfluidic device fabrication procedure for which I need the silicon wafers: to get the desired microfluidic patterns we first thermally grow the silicon dioxide (>500 nm) on the silicon wafers > then do the HF etching to remove unwanted silicon dioxide from photolithographically processed wafers > then dice the wafers to get chips > and finally etch the bare silicon chips with silicon dioxide patterns at 70 degree C for 40 minutes using 40 % potassium hydroxide to remove the specific amount of silicon.

We need silicon wafers very frequently and had worked with another company before for many years. But recently we had the following few problems with their wafers, and that's why we are now planning to switch the vendor:

1. First problem was cutting those wafers using the pen type diamond cutter. Usually the pen shape cutter has worked well in the past, but last few times it did not. We thought the problem could be because the wafers were either very thick or not the specified <100> orientation, so we had to use the cleanroom dicing saw to cut through the wafers and get individual chips.

2. Second problem was with the etch rate. Following the above mentioned etching procedure usually we get (and need) >30 um feature height after etching. However with the last few batches the etch rate was terribly slow, and we had got barely < 5 um feature height even with the overnight etching. Considering the poor etch rate it seemed like the wafer orientation might be <111> but not the <100> that was mentioned in the order.

Now we believe the following specifications: four inch single side polished silicon test wafers; N<100> any res; any thickness; any type/dopant; any back surface; any flats should work for us (and has worked in the past). So considering the above discussion if you could confirm that the unknown problem should be solved with the wafers from your company then I would be ready to place the initial order of 25 wafers.


UniversityWafer, Inc. Quoted:

Here are my comments regarding regarding your problems:

  1. Place a wafer on a soft surface, press in the middle with a ball-point pen tip until it breaks.
    If it breaks at right angles then it is (100), if it breaks at 60º/120º then it is (111), if it breaks at 79.5º/109.5º angles then it is (110). If it does not break at well defined angles then it is not monocrystalline.
  2. One problem with some etch solutions is that etch rate is affected by Oxygen content. The etch has to neutralize dissolved Oxygen before it can attach Silicon. Of course if wafers are of wrong
  3. orientation then they will etch differently.
  4. Do not use low resistivity wafers. At very high dopant levels the dopant does affect etch rate. Stick to wafers with Ro>1 Ohmcm.
Item Material Ori Diam (mm) Thick (μm) Surf. Res Ωcm Comment
O362 n-type Si:P [100] 4" 525 P/E 3.5-8.1 SEMI Prime, 2Flats, TTV<4μm, Bow<15μm, Warp<30μm, Epak cst

Reference #213267 for specs and pricing.