300nm Thermal Oxide on Silicon Wafers

university wafer substrates

SiO2 Coated Silicon Wafers to Fabricate Nanostructers

A PhD researcher requested the following:

We are working on nanostructures made of silicon. Usually, the thickness of silicon film ranges from 300nm to 700nm in our research. The substrate can be SiO2 or other transparent insulators. Do you think it is possible to provide silicon film at this thickness range?

Reference #205719 for specs and pricing.

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What Substrates are Used for Optical Characterization with Ellipsometry?

A solar development engineer requested the following:


I am looking at Thermal Oxide Wafer with ID 1455 (it has 300 nm thermal oxide, SSP). Do these have thermal oxide on both sides? Can these wafers be used for optical characterization with ellipsometry of layers deposited on top? I am also interested in Silicon wafer (SSP) with ID 695. Can these wafers be used for optical characterization with ellipsometry of layers deposited on top? And Silicon wafers (SSP) with ID 590 have in their description, “Silicon wafers Test Grade. Used as supporting substrate for AFM, XRD and SEM Testing. And used for scientific research purpose Use items as substrates to prepare research samples.”. Does this mean they may have contamination from prior experiments? Also, these are TEST grade, what does that mean? Can you please send me a quote for 50 wafers each? 


Yes, thermal oxide coated silicon wafers can be used for optical characterization with ellipsometry of layers deposited on top. Test grade just means the tolerances are not as tight as prime grade.
No contamination.


What Are 300nm SiO2 Coated Silicon Wafers Used For?

300nm thermal oxide coated silicon wafers are commonly used as substrates to fabricate self-assembled monolayers (SAMs). The oxide layer provides a surface that is easy to functionalize with various chemical groups that can anchor the molecules in the SAM.

The thermal oxide layer on the silicon wafer surface provides insulation, passivation, and protection to the underlying material. This layer can also serve as a gate oxide in MOS (metal-oxide-semiconductor) devices, which are commonly used in integrated circuits and other electronic components.

In addition, the thickness of the thermal oxide layer can be tailored to achieve specific electrical properties and to meet the requirements of different applications. For example, thicker oxide layers may be used in power devices, while thinner layers may be used in high-speed devices.

Overall, silicon wafers with 300 nanometers of thermal oxide are a versatile and important material in the field of microelectronics and semiconductor manufacturing.

Below are some examples of uses for 300nm thermal oxide substrate uses.

Why is 300nm Oxide Purple in Color?

The color purple is a result of a specific range of wavelengths of light that are absorbed and reflected by an object or substance. In the case of visible light, which is the portion of the electromagnetic spectrum that is visible to the human eye, the color purple has a wavelength of approximately 380-450 nanometers.

300 nanometers of thermal oxide

When light falls on an object or substance, the wavelengths that are absorbed by the material are subtracted from the visible spectrum, while the wavelengths that are reflected back to the eye determine the color that is perceived. In the case of purple, the material is absorbing most of the wavelengths in the green-yellow range of the spectrum, while reflecting the shorter wavelengths in the blue-violet range.

It's worth noting that the perception of color is also influenced by factors such as lighting conditions, the angle of observation, and the sensitivity of an individual's eyes. Additionally, different materials and substances may appear to be slightly different shades of purple due to variations in their molecular structures and optical properties.


Self Assembled Monolayer

Item #2284 - 50.8mm P<100> 0-100 325um SSP Test Grade w/ 300nm Thermal Oxide. Thickness Tolerance+/-15%. Used for Self-Assembled Monolayer (SAM).

Thermal Oxide Wafer For Mounting Exfoliated 2D Samples

An applied physics postdoctoral scholar requested the following quote:

Hello, please could you provide me a quote for: - 3x 100mm diameter, undoped (high resistivity), 500 or 525um thick, single side polished, silicon wafers - 2x 100mm diameter, doped (low resistivity), 500 or 525um thick, single side polished, silicon wafer with 300nm thermal oxide SiO2.

The quote was for five wafers total: 3 undoped and 2 with thermal oxide. Is that possible?

I am looking to use the wafers for two purposes, so perhaps you can advise if I chose the right ones from your stock list. I plan to use the undoped wafers to make sample plates for holding samples in a cryostat. We will use photolithography lift-off to make some metallic contacts, then dice up the wafer into smaller sample plates where samples can be mounted and wire bonded to, such that electric contact can be make in the socket on the cryostat. Perhaps ID num 3328 would work for this.

For the thermal oxide wafer we plan to mount exfoliated 2D samples and use the oxide as a gate dielectric. Perhaps ID num 1583 would work.

Fabricating Sensing Device

Researchers have used the following item to fabricate sensing devices.

Item #1428 - 76.2mm P/B (100) 1-10 ohm-cm 380um Prime with 300nm of wet thermal oxide.


300nm wet thermal oxide Researchers have used for microscopy (optical, AFM, SEM etc.) imaging of various materials.

Item #1432 - 100mm P/B (100) 1-10 ohm-cm 500um SSP Prime Grade with 300nm of Thermal Oxide

Thin Film Deposition

300 nanometer of Wet Thermal Oxide for sputtering and r thin film deposition.

Item #1433 - 100mm N/PH (100) 1-10 ohm-cm 500um SSP Prime with 300nm of Oxide

Fabricate Organic Electronc Devices

300nm Wet Thermal Oxide with Thickness Tolerance +/- 7% used to fabricate organic electronic devices for academic research.

Item #1583 - 100mm P/B (100) 0.001-0.005 ohm-cm 500um SSP Prime Grade with 300nm of Thermal Oxide

In-Situ Sputtering

300nm Wet Thermal Oxide, AND: In-situ sputter etch followed by sputter deposition of 200Å Ti and 2,000Å Pt.

Item #2865 - 100mm P/B (100) 1-10 ohm-cm 500um SSP Test Grade with 300nm of Thermal Oxide

What Thermal Oxide Coated Silicon Wafers Used to Deposit Graphene fFake by Mechanical Exfoliation Method?

A PhD student requested the following quote:

I am looking for high quality single crystal Silicon substrates orientated to 100 face. -Only single side oxide (sio2) 300 nm thickness. -Substrate dimension is 5*5*0.5 mm3, ie wafer thickness is 0.5 mm. (500 micrometer thickness) -Only single side should be polished which is Sio2 side. (what I mean here is that Only single side of Si substrate should be polished before growing the thermal oxidization sio2. It is important polish the surface of pure single crystal silicon (100 orientation) and then, thermally oxidized at temperature of about 1050 C in dry, clean, 99.9999% pure O2 environment). -Obtaining as mush as possible fine, smooth and homogeneous SiO2 surface. -The other side of Si substrate should be etched and then coated with pure Aluminum source (thickness ± 80 nm). -Alignment markers should be conducted on SiO2 surface so that I can deposit graphene flake by mechanical exfoliation method on top of the surface later on. What I mean is that array of predefined digit crosses ➕ should be made on sio2 surface - (whole wafer or chip) called as alignment markers. There are two kind of crosses, big and small crosses. The distance between two big crosses is about 180 micrometre in both directions (vertical and horizontal directions). Each big cross size is about 20 micrometre. The small ones are located between the two big crosses. The distance between every two small crosses is about 60 micrometre. Each small cross size is about 10 micrometre. All cross features should be numbered (each cross has special number so I can use them as Map Coordinates to identify and locate the proper graphene location under optical microscope and also for further fabrication process). The deposited material of alignment markers should be as gold Metal markers to give enough contrast while they are seen under the optical microscope (50 nm thickness is recommended). They are usually done by Electron beam lithography (EBL). After doing alignment markers, substrate should be cleaned and O2 direct plasma shing should be used for cleaning as well. -Recommended resistivity of whether is p- type or n- type Silicon wafer requires 10 k ohm.cm I appreciate your assistance and I hope to hear from you soon. If you have further inquiries or suggestions, please let me know.

UniversityWafer, Inc. Quoted:

Item   Qty.   Description
HJ00b. 3   Silicon wafers, per SEMI Prime, Oxide+Si(SSP) 4" (100.0±0.5mm)Ø×525±15µm,
                   Diced into 10mm x 10m squares,
                   FZ p-type Si:B[100]±0.5°, Ro > 10,000 Ohmcm,
                   One-side-polished, back-side etched,
                   Front side with dry thermal oxide: ~300nm,
                   SEMI Flat (one),
                   Approx. 60 squares per wafer,
                   Blue tape and sealed in single wafer cassettes.

Item   Qty.   Description
HJ00c. 2   Silicon wafers, per SEMI Prime, Oxide+Si(SSP) 4" (100.0±0.5mm)Ø×525±15µm,
                   Diced into 5mm x 5m squares,
                   FZ p-type Si:B[100]±0.5°, Ro > 10,000 Ohmcm,
                   One-side-polished, back-side etched,
                   Front side with dry thermal oxide: ~300nm,
                   SEMI Flat (one),
                   Approx. 250 squares per wafer,
                   Blue tape and sealed in single wafer cassettes.

Reference #259347 for pricing.