We propose the use of silicon wafers to improve light absorption and improve the conversion efficiency of silicon solar cells. The gap between the current state of the art in silicon photovoltaics and the next generation of solar cells has widened due to the success achieved in the development of highly efficient silicon PV cells in recent years.
Researchers have discovered that the thinner a silicon wafer is the more efficient.
Ask for Item#253540
2” and 3” diameter, float-zone, Si(100), n-type 1-5 Ohm-cm 20 microns thick
Researchers asks: I was just wondering whether the “Solar” products have a PN junction already (i.e. product ID 2920). If not, do you stock any products with a PN junction?
1) For solar application, P/N junction is typically made with a diffusion process. We do have a diffusion facility capable of creating junctions on wafers with diameter up to 4". Please let us know if you are interested in going into the project on a smaller diameter wafers.
2) We also have Si wafers with P/N junctions created by silicon on silicon epitaxial deposition method. Please ask for our inventory.
A researcher asked the following:
I want 4 inch silicon wafers p-doped to ~10^15-10^16 cm^-3. The doping concentration is a bit flexible as long as it's not above 10^18 cm^-3. We don't have a strict requirement of thickness but ~200 um would be better. But the top surface has to be heavily n-doped to form n+ emitter. This is the minimum requirement for our wafers. In addition, if it is possible to heavily p-dope the back surface of the wafer to form ohmic contact, that would be great as well. If this kind of wafer is readily available at University wafers, we would like to order quickly. If it is not readily available but possible to prepare within a few days, please let me know that as well. Depending on the price per wafer, we will order a few.
Item Qty. Description
GX82. 25 Solar cell silicon wafers, per SEMI Prime, P/P 4"Ø×300±25µm,
p-type Si:B±0.5°, Nc=(3.05-1.50)E15/cm³, Ro=(5-10)Ohmcm,
With Diffused Phosphorus layer ~1 µm thick, of Nc=(3-10)E18/cm³, Ro~(0.005-0.012)Ohmcm}
SEMI Flats (two),
Sealed in Empak or equivalent cassette,
Note: Please see the pictures for the surface after process.
Price: $ Please contact us.
Photo of the wafer after our diffusion process. We expect a similar surface now.
Silicon heterojunction solar cells (SHJ), which consist of N-silicon wafers (Cz), have aroused growing industrial interest. The low efficiencies can be achieved by using low-cost, high-efficiency silicon cells, and the cheap silicon can also be used to form SH J cells.
The work uses a Monte Carlo simulation approach that allows us to take into account uncertainties regarding the performance of different types of silicon wafers and their properties. We identify the most important factors influencing commercial comparison between wafer types.
N-type wafers achieve the same efficiency as SHJ solar cells with a different silicon wafer type. Our analysis suggests that the p-types of SHj solar cells should be at least twice as efficient as their n-types. This work represents a new approach to the production of SH-Joules per square centimeter (n - p) of SH-J cells from p- type wafer waves.
Summary of Solar Cell Production, and Limiting Efficiency of Silicon Solar Cell
It has been well established that the limiting efficiency of single crystals falls at about 29% [Swanson] this limit was established in the seminal work by Tiedje. In figure 1 we can see this limiting efficiency as a function of solar cell thickness. In this diagram, the peak efficiency is shown to be 29% with a thickness of just under 100µm.
Typical production solar cells achieve about 20% efficiency, while the best laboratory efforts have achieved about 25% [Swanson]. Green provides an excellent summary of the current progress of high-efficiency single-crystal silicon solar cells, and reconfirms the 29% limit established by Tiedje.
The process of manufacturing solar cells from single crystal p-type silicon wafers is detailed below. This is the generalized method used based on a number of sources. It should be noted that different companies have different patented, and trade secret processes for each of these steps, but the steps remain the same.
After an initial cleaning procedure, the wafer is textured to create pyramid-like structures on the surface of the silicon. This causes incoming sunlight reflected off of one pyramid to bounce into other pyramids on the surface improving the overall sunlight absorption rate.
N doping (usually Phosphorous):
A variety of methods are used to dope the top surface of the P-type wafer to create N-type regions. This process (typically gas diffusion in a high-heat furnace) creates the critical p-n junction which forms the permanent electrical field.
Edge diffusion cleaning:
The doping process causes the phosphorous dopant to diffuse to the edges of the wafer, if this excess dopant was allowed to remain it would cause short circuiting between the positive and negative contacts of the solar cell. The excess dopant is removed by an acid-etching procedure.
The wafer is then given an anti-reflective coating, usually silicon nitride, to improve absorption.
Screen printing of front and rear surface contacts
In the final step of the production process, front and rear surface contacts are screen printed onto the surface of the wafer to create the positive and negative contacts of the solar cell. The solar cells are then ready to be wired together to create solar panels.
1.) Tiedje et al; Limiting Efficiency of Silicon Solar Cells: https://optoelectronics.eecs.berkeley.edu/ey1984ieeeed315.pdf
2.) M.A Green; Progress and outlook for high-efficiency crystalline silicon solar cells https://126.96.36.199/FT/957/22841/412931.pdf
3.) Swanson, R.M; Approaching the 29% limit efficiency of silicon solar cells
4.) Solar Cell production process https://www.photonics.com/Article.aspx?AID=40098
5.) Solar cell production video: https://www.youtube.com/watch?v=TRATu_wEgAY
6.) Solar Cell production video: https://www.youtube.com/watch?v=fZ1SC-vUe_I
We have the following 156.75mm x 156.75mm +/-0.25mm substrates.
|Dimension||156.75mm x 156.75mm + 0.25mm|
|Diagonal||210mm + 0.5mm (Round Chamfers)|
|Thickness||200um + 20um|
|Front||Anisotropically texturized surface and dark silicon nitride anti-reflection coatings|
|0.7mm silver busbars|
|Back||local aluminum back-surface field|
|1.7mm (silver/aluminum) discontinuous solderng pads|
|Production and Quality Control|
|Precision cell efficiency sorting procedures|
|Stringent criteria for color uniformity and appearance|
|Reverse current and shunt resistance screening|
|ISO9001, ISO14001, and OHSAS 18001 certificated|
|Calibrated against Fraunhofer ISE|
|Max. Power Current||9.29||9.26||9.24||9.22||9.2||9.19|
|Max. Power Voltage||0.568||0.567||0.566||0.564||0.563||0.562|
|Max Power Current||9.16||9.14||9.12||9.07||9.03||8.99|
|Short Circuit Current||9.64||9.62||9.6||9.56||9.52||9.49|
|Max Power Voltage||0.56||0.559||0.557||0.555||0.552||0.55|
|Open Circuit Voltage||0.661||0.66||0.658||0.656||0.654||0.652|
|Current Temp Coefficients||0.04%/C|
|Voltage Temp Coefficients||-0.32%/C|
|Power Temp Coefficients||-0.42%/C|