Substrates for Integrated Circuit Design (IC)

What is IC Design?

Integrated Circuit (IC) design is the process of creating microelectronic circuits—essentially the "brains" inside electronic devices—on a semiconductor substrate, usually silicon. This includes everything from designing the logic of a microprocessor to laying out analog circuits for amplifiers or sensors.

🧠 What is IC Design?

IC design involves conceptualizing, simulating, verifying, and laying out the microscopic components of a chip such as:

• Transistors

• Capacitors

• Resistors

• Interconnects (wiring)

These components are fabricated together on a single piece of semiconductor material, forming what's called an integrated circuit.

👷‍♂️ Key Job Titles in IC Design

Here’s a breakdown of common job roles in the field:

1. Digital IC Design Engineer

• Focus: Design of digital logic circuits (e.g., CPUs, GPUs, ASICs).

• Tools: Verilog/VHDL, SystemVerilog, RTL design, synthesis tools like Synopsys or Cadence.

• Tasks: Design of logic blocks, clock gating, power optimization, verification support.

2. Analog IC Design Engineer

• Focus: Circuits handling real-world signals (e.g., amplifiers, ADCs, DACs, PLLs).

• Tools: SPICE simulation, Cadence Virtuoso.

• Tasks: Transistor-level design, layout, matching, and noise/power optimization.

3. Mixed-Signal IC Designer

• Focus: Combines analog and digital (e.g., data converters, RF front ends).

• Tasks: Interface circuits, analog-digital boundary design.

4. Physical Design Engineer

• Focus: Back-end design – placing and routing the chip layout.

• Tools: Cadence Innovus, Synopsys ICC2.

• Tasks: Floorplanning, placement, routing, timing closure, power planning.

5. Verification Engineer

• Focus: Ensures chip designs work as intended before fabrication.

• Tools: SystemVerilog, UVM, formal verification tools.

• Tasks: Create testbenches, simulate and debug RTL designs.

6. DFT (Design for Test) Engineer

• Focus: Insert and verify test structures like scan chains and BIST (built-in self-test).

• Tools: Tessent (Mentor), Synopsys DFT Compiler.

7. Packaging Engineer

• Focus: Physical encapsulation and I/O design of chips.

• Tasks: Wire bonding, flip-chip design, thermal/electrical modeling.

8. EDA Tool Developer

• Focus: Develop software tools used by all the above engineers.

• Background: Strong CS/math skills; may work at Cadence, Synopsys, or Mentor.

🧪 What Substrates Are Used?

The substrate is the base material where all the devices are built. Here's what’s common:

🏭 IC Design Process: Overview

1. Specification – What the chip is supposed to do.

2. Architecture – Block-level design.

3. RTL Design – Logic description (mostly digital).

4. Simulation & Verification – Ensure correctness.

5. Synthesis & Layout – Transform design into geometry.

6. DFT Insertion

7. Tape-out – Final design sent to fabrication.

8. Fabrication – Made at a foundry (e.g., TSMC, Intel).

9. Testing – Wafer probe, packaging, final test.

Integrated Circuit Design Work Flow

Here is a detailed look at the IC design flow—from an idea in someone’s head to a chip running in your smartphone. It’s a mix of engineering, science, and art, really.

🛠️ Step-by-Step IC Design Flow

1. Specification Phase

• Goal: Define what the chip will do.

• Inputs: Market needs, product goals, power, area, and performance targets.

• Output: A written spec detailing features (e.g., "A 32-bit RISC-V core with 1GHz clock speed, <1W power").

2. Architecture Design

• Goal: Design the block-level structure of the chip.

• What Happens:

  • Partition the design into functional blocks (CPU core, memory, I/O, etc.)

  • Choose data paths, control logic, memory architecture

  • Early performance & power estimation

3. RTL Design (Register Transfer Level)

• Tools: Verilog, VHDL

• Goal: Code the chip logic at a high abstraction.

• Example:

  verilog
  
          
   
          
  always @(posedge clk) begin   if (reset) counter <= 0;   else counter <= counter + 1; end 
                        

• Engineers: Digital Design Engineers

4. Functional Verification

• Goal: Make sure the RTL does what it’s supposed to.

• Tools: SystemVerilog, UVM, Questa, VCS

• Methods: Simulation, testbenches, assertions, coverage

• Bonus: Formal verification (mathematical proof of correctness)

5. Synthesis

• Goal: Convert RTL to gate-level (real logic gates)

• Tools: Synopsys Design Compiler, Cadence Genus

• Output: Netlist (standard cells mapped to a tech library)

6. Place and Route (Physical Design)

• Goal: Physically lay out the gates and wires

• Sub-steps:

  • Floorplanning: Place large blocks (memory, I/O, etc.)

  • Placement: Place logic gates

  • Clock Tree Synthesis: Balance timing across chip

  • Routing: Connect everything with metal layers

• Tool: Cadence Innovus, Synopsys ICC

7. Timing Analysis & Optimization

• Goal: Ensure signal timing meets clock constraints

• Tools: PrimeTime, Tempus

• Checks:

  • Setup and hold time violations

  • Slack analysis

  • IR drop, signal integrity

8. DFT (Design for Test)

• Goal: Insert test structures to allow chip testing after fab

• Tools: Mentor Tessent, Synopsys DFT Compiler

• Includes: Scan chains, BIST, boundary scan

9. Tape-out

• Goal: Create the final files (GDSII or OASIS) sent to a foundry like TSMC, Intel, or GlobalFoundries.

• This is the big milestone before fabrication.

10. Fabrication

• Substrate Used: Usually silicon wafers, sometimes SOI or GaAs.

• Process: Optical lithography, ion implantation, etching, CMP, etc.

• Output: Bare silicon dies on a wafer.

11. Packaging and Testing

• Die Packaging: Into a chip (e.g., BGA, QFN, Flip-Chip)

• Testing:

  • Wafer-level test (probe)

  • Post-package functional test

  • Burn-in testing for reliability

🚀 After All That… It Ships!

Now your design becomes part of:

• A phone

• A car

• A data center server

• A satellite

• Or something in your microwave or coffee machine 😄

🧑‍💼 Who Does What Again?

What is Photonic Integrated Circuit Design?

Photonic Integrated Circuit (PIC) design is the process of creating chips that use light (photons) instead of, or alongside, electricity (electrons) to perform functions like data transmission, signal processing, or sensing. It’s like designing an electronic chip (IC), but for optical components.

🔍 What Is a PIC?

A Photonic Integrated Circuit integrates multiple optical components — such as lasers, modulators, detectors, and waveguides — onto a single chip, much like an electronic IC integrates transistors, capacitors, and resistors.

🧩 Key Components on a PIC:

🛠️ PIC Design Workflow:

1. System Specification
   Define optical/electrical performance targets, e.g., wavelength range, data rate.

2. Component Selection
   Choose or design lasers, waveguides, detectors, etc., depending on application (telecom, lidar, biosensors, etc.).

3. Layout Design
   Use specialized EDA tools like Luceda, Synopsys OptoDesigner, or Photon Design to build the chip layout.

4. Simulation & Modeling
   Simulate optical behavior using tools like Lumerical to verify losses, coupling, reflection, and signal integrity.

5. Fabrication
   Chips are fabricated on platforms like Silicon Photonics (SiPh), Indium Phosphide (InP), or Silicon Nitride (SiN).

6. Testing & Packaging
   Align optical fibers, test insertion loss, bandwidth, and thermal stability.

🔬 Applications of PICs:

• 📡 Telecommunications / Datacom – High-speed optical transceivers

• 💻 AI & HPC – Optical interconnects for faster data transfer

• 🚘 Lidar – For autonomous vehicle sensing

• 🧪 Biosensing – Label-free detection of biomolecules

• ⚛️ Quantum Photonics – Integrated platforms for qubit communication

🧠 Who Designs PICs?