Gallium Nitride on Silicon Epitaxy Wafer 

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GaN-on-Silicon Epitaxy Wafers for Power & RF

UniversityWafer, Inc. supplies GaN-on-Si epitaxy wafers engineered for high-voltage power electronics and RF power devices. Stacks typically start on Si(111) silicon wafers with an AlN nucleation layer, graded AlGaN buffers (or superlattices) to manage stress and dislocations, followed by the GaN device layers (e.g., AlGaN/GaN HEMT, p-GaN gate e-mode). We support 100–200 mm diameters with attention to warp/bow and TTV for downstream lithography and yield.

Need GaN-on-Si Epitaxy Wafers Fast?

We supply 100–200 mm Si(111) wafers with AlN buffers, graded AlGaN stacks, and GaN HEMT device layers ready for power & RF fabrication. Get your quote or custom spec today.

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Where GaN-on-Si Excels

  • Power switching (100–650 V+): Fast chargers, server/telecom PSUs, PV, motor drives.
  • RF power: 5G mMIMO, phased-array radar, satcom front-ends.
  • Manufacturing scale: 150–200 mm lines help reduce die cost vs native GaN substrates.

Quick Spec Template (Copy/Paste)

  • Diameter / Orientation: 150 mm Si(111) DSP (TTV ≤ ___ µm; bow/warp ≤ ___ µm)
  • Substrate Thickness: ___ µm; Resistivity: ___ Ω·cm
  • Nucleation: AlN ___ nm @ LT
  • Buffer: step-graded AlxGa1-xN ___ µm (or superlattice); leakage target: ___
  • Channel: GaN ___ µm; mobility / ns targets: ___ / ___
  • Barrier: AlxGa1-xN (x = ___); thickness ___ nm
  • Cap/Mode: p-GaN gate (e-mode) or Schottky (d-mode); VTH target: ___
  • Passivation: SiN ___ nm; surface RMS target: ___ nm
  • Reliability targets: BV, RDS(on), fT/fmax, SOA

Quality & Process Considerations

  • Bow/warp control: Buffer design minimizes thermal-mismatch stress for 150–200 mm handling.
  • Threading dislocations: Low TDD improves leakage and long-term reliability.
  • Surface & passivation: Smooth surfaces and robust SiN/oxide passivation support stable RF and power operation.
  • Backside & thickness: Substrate thickness and backside prep influence thermal path and wafer stability.

What Is GaN-on-Silicon (GaN-on-Si)?

GaN-on-Si refers to gallium-nitride epitaxial stacks grown on silicon substrates (typically Si(111)), combining the wide-bandgap, high‐electron-mobility and high-breakdown strength of GaN with the cost-effective, large-diameter infrastructure of silicon. The heteroepitaxy inherently introduces lattice and thermal expansion mismatches, which are managed through engineered buffer and nucleation layers.

Why It Matters for Power & RF

Because GaN enables higher breakdown voltage, faster switching, and better thermal stability than silicon alone, GaN-on-Si wafers are increasingly used for:

  • High-voltage power devices (≥ 100 V, 650 V, even 1200 V class) for server PSUs, EV chargers, renewables.
  • RF and microwave HEMTs (e.g., 5G mMIMO, radar) where GaN’s high fT/fmax and high power density make a difference.
  • Integration with silicon CMOS or large diameter manufacturing (100 mm → 150 mm → 200 mm) to reduce wafer cost. :contentReference[oaicite:1]{index=1}

Typical Epi Stack & Substrate Options

Key layers in a GaN-on-Si epi stack include:

  • Si substrate: commonly Si(111) DSP, diameters 100 mm, 150 mm or 200 mm. Tight TTV, warp/bow control is critical for downstream processing.
  • AlN nucleation layer: A thin AlN layer grown at low temperature to isolate direct interface mismatch and avoid melt‐back etching of silicon. :contentReference[oaicite:2]{index=2}
  • Graded AlGaN / superlattice buffer: A multi-step AlₓGa₁₋ₓN buffer (or superlattice) that gradually transitions lattice and thermal expansion mismatch, reduces threading dislocations and controls bow/stress. :contentReference[oaicite:3]{index=3}
  • GaN channel / drift / device layer: The main functional GaN layer (HEMT channel, drift region) grown on the buffer. Its thickness and doping depend on device class (RF vs power).

Technical Targets & Manufacturing Challenges

When specifying GaN-on-Si wafers, pay attention to:

  • Wafer bow/warp: Bow can impact lithography overlay and device yield — stacked buffers must compensate thermal stress during cooldown. :contentReference[oaicite:4]{index=4}
  • Threading-dislocation density (TDD): High TDD in GaN leads to reliability issues (leakage, breakdown). Premium epi stacks aim for ~10⁸–10⁹ cm⁻². :contentReference[oaicite:5]{index=5}
  • Buffer leakage and breakdown: The buffer stack must block vertical current and sustain high breakdown fields (MV/cm) while minimizing traps. :contentReference[oaicite:6]{index=6}
  • Thermal management: Since GaN has higher dissipation, the choice of Si substrate thickness, backside metallization, and wafer bow affect thermal reliability.

Ordering & Available Options

UniversityWafer offers GaN-on-Si wafers with customizable parameters to meet your application:

  • Diameter: 100 mm / 150 mm / 200 mm Si(111)
  • Substrate spec: DSP polish, high resistivity option; wafer thickness matched to process line.
  • Epi stack customization: Standard buffer + GaN device layer or full device-ready stack depending on your foundry/epigrower.