We are fabricating the QD laser and below picture is our EPI structure. We would like to purchase some Si-Gallium Arsenide (GaAs) for developing the fabrication process (used as dummy wafer). 4 inch wafer. Do you have some suggestion?
GaAs Wafers for QD Laser Fabrication
A postdoctoral fellow, working in a integrated photonics lab requested the following quote.

Reference #318703 for specs and pricing.
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What Substrates Are Used for Quantum Dot Laser Fabrication?
Quantum dot (QD) laser fabrication commonly uses GaAs wafers, silicon substrates, and other III-V semiconductor materials for integrated photonics, optoelectronics, and advanced semiconductor device research. Selecting the correct wafer specifications is critical for epitaxial growth, electrical performance, thermal management, and device reliability.
A postdoctoral research fellow requested guidance for selecting suitable doped silicon wafers for QD laser process development and integrated photonics fabrication.
“We do research involving quantum dot laser fabrication and would like to purchase silicon doped wafers for process development. Could you recommend a suitable 4-inch wafer and provide a quotation?”
Recommended Silicon Wafer Specifications for QD Laser Research
Researchers developing III-V/Si photonics, integrated photonics devices, and quantum dot lasers often use high-purity silicon wafers with carefully selected doping concentrations and surface finishes to support epitaxy, photolithography, etching, and semiconductor process integration.
A typical starting point for many quantum dot laser fabrication projects includes:
Recommended 4-inch (100 mm) Silicon Wafer Parameters
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Wafer Diameter and Thickness
- 100 mm (4-inch) silicon wafer
- SEMI standard thickness of approximately 525 ± 25 µm
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Crystal Orientation
- <100> orientation for semiconductor device fabrication and epitaxial growth
- Widely used in integrated photonics and optoelectronic device processing
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Doping Type and Resistivity
- N-type silicon wafers with phosphorus or arsenic doping are commonly used for quantum dot laser fabrication because they provide strong electrical conductivity and support ohmic contact formation.
- Typical resistivity range: 1–10 Ω·cm corresponding to doping concentrations near 1015–1016 cm-3.
- Lower resistivity wafers (0.001–0.01 Ω·cm) may be selected for applications requiring reduced substrate resistance.
- Higher resistivity wafers (10–20 Ω·cm) may help reduce leakage current and electrical crosstalk in photonic semiconductor devices.
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Wafer Growth Method
- Float Zone (FZ) silicon wafers are preferred for many photonics applications because of their high purity and low oxygen content.
- Czochralski (CZ) silicon wafers are more affordable and widely available for semiconductor process development.
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Surface Finish
- Single Side Polished (SSP) wafers are suitable for standard front-side device fabrication.
- Double Side Polished (DSP) wafers are beneficial for backside processing, wafer bonding, and advanced photonic integration.
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Wafer Grade
- Prime Grade silicon wafers provide tighter specifications for TTV, flatness, and surface quality.
- Test Grade wafers may be suitable for early-stage process development or lower-cost fabrication testing.
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Additional Semiconductor Processing Parameters
- Tight TTV specifications may be required for advanced lithography alignment and epitaxial growth uniformity.
- Surface cleanliness is critical for MBE and MOCVD growth processes used in III-V semiconductor epitaxy and QD laser fabrication.
Typical Quantum Dot Laser Wafer Configuration
A common baseline wafer used for QD-laser-on-silicon research includes:
- 4-inch diameter silicon wafer
- <100> crystal orientation
- N-type phosphorus doping
- 1–10 Ω·cm resistivity
- Float Zone (FZ) growth
- 525 ± 25 µm thickness
- Single Side Polished (SSP) prime grade surface
- TTV ≤ 10 µm
These specifications provide a high-quality silicon substrate suitable for III-V epitaxy, integrated photonics, quantum dot laser fabrication, and advanced semiconductor device processing.
Researchers may also integrate III-V semiconductor layers onto silicon wafers for next-generation photonic integrated circuits, optical communication systems, and optoelectronic semiconductor devices.
Reference #318482 for specifications and pricing.