High-Quality Silicon Wafers for Research & Advanced Applications
UniversityWafer supplies high-quality silicon wafers engineered to meet the mechanical, electrical, and surface specifications required by modern research labs, pilot lines, and production environments. From small-diameter R&D wafers to large-format substrates, our silicon wafers are selected to support reliable processing and reproducible results.
Wafer quality directly affects yield, device performance, and process stability. Tight control of thickness, flatness, surface polish, resistivity, and contamination helps reduce process variation and minimizes the risk of costly rework or failed runs.
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Available Silicon Wafer Specifications
We offer silicon wafers across a wide range of sizes and quality levels to support university research, government labs, startups, and established manufacturers:
- Diameters:
1″ (25 mm)
2″ (50.8 mm)
3" (76.2 mm)
4″ (100 mm)
5" (125 mm)
6″ (150 mm)
8″ (200 mm)
12″ (300 mm)
- Thickness options with controlled Total Thickness Variation (TTV)
- Single-side polished (SSP) and double-side polished (DSP) surfaces
- Undoped, P-type, and N-type silicon
Crystal Growth Options: CZ and FZ Silicon
Both Czochralski (CZ) and Float Zone (FZ) silicon wafers are available, allowing you to match material purity and electrical behavior to your application:
- CZ Silicon: Cost-effective, supports larger diameters, widely used for CMOS and MEMS
- FZ Silicon: Lower impurity content, preferred for high-resistivity, RF, and power devices
Electrical Properties & Resistivity Control
Electrical specifications such as dopant type and resistivity are tightly controlled to ensure predictable device behavior. Common resistivity ranges support applications including logic devices, RF structures, sensors, and photonics.
For experiments requiring consistent electrical performance, lot-level resistivity control and optional verification help maintain confidence across multiple runs.
Surface Quality, Flatness & Polish
Surface finish and flatness are critical for lithography, bonding, and thin-film deposition. Single-side polished wafers are suitable for many standard processes, while double-side polished wafers provide superior flatness and thickness uniformity for advanced applications such as SOI bonding and photonics.
Quality wafers are specified using metrics such as bow, warp, and Total Thickness Variation to help ensure stable handling and uniform processing.
US Inventory & Custom Wafer Solutions
UniversityWafer maintains US-based inventory for many common silicon wafer configurations, helping reduce lead times and sourcing uncertainty. Custom specifications including specialty diameters, tight flatness targets, and unique doping profiles are also available upon request.
Whether you are prototyping a new device or preparing to scale a process, our team can help you identify silicon wafers that meet your quality requirements without overspending on unnecessary specifications.
Related Resources
- Silicon Wafers – Overview of silicon wafer types, sizes, and research applications.
- Silicon Wafer Resistivity Guide – Learn how resistivity affects electrical performance and device behavior.
- Float Zone Silicon Wafers – Low-impurity silicon for high-resistivity, RF, and power applications.
- Silicon-on-Insulator (SOI) Wafers – Substrates engineered for isolation, photonics, and advanced device structures.
- Photonics Engineering Substrates – Wafer specifications tailored for silicon photonics and optical devices.
- 100 mm Silicon Wafers – Common wafer size for university labs and early-stage prototyping.
- 150 mm Silicon Wafers – Mid-scale wafers for advanced research and pilot production.
What Defines a High-Quality Silicon Wafer?
A high-quality silicon wafer is defined by a combination of mechanical, electrical, and surface specifications rather than by diameter alone. In research and production environments, quality determines how reliably a wafer can move through lithography, etching, deposition, and bonding without introducing defects or variability.
Key quality indicators include thickness control, flatness, surface polish, crystal purity, and contamination limits. Together, these parameters influence yield, device performance, and reproducibility across an entire process flow.
Why Thickness and TTV Matter
Thickness uniformity is critical for maintaining consistent focus and film thickness during processing. Metrics such as Total Thickness Variation (TTV) describe how much the wafer thickness varies from edge to edge. Lower TTV values support tighter process control, especially for advanced lithography and wafer bonding applications.
As wafer diameter increases, thickness control becomes even more important. Larger wafers require stricter tolerances to ensure mechanical stability and uniform processing across the full surface.
Crystal Growth and Material Purity
Silicon wafers are commonly produced using either Czochralski (CZ) or Float Zone (FZ) crystal growth methods. CZ silicon is widely used due to its availability in large diameters and broad resistivity ranges, while FZ silicon offers lower impurity levels and is often chosen for high-resistivity, RF, and power applications.
Selecting the appropriate crystal type helps balance electrical performance, defect density, and cost depending on the intended application.
Surface Finish and Flatness
Surface polish plays a major role in wafer quality. Single-side polished (SSP) wafers are suitable for many CMOS and MEMS processes, while double-side polished (DSP) wafers offer superior flatness and thickness control for bonding, photonics, and precision metrology.
Flatness specifications such as bow and warp are used to quantify wafer deformation. Tighter flatness improves lithography alignment, depth-of-focus margins, and etch uniformity in demanding processes.
Electrical Specs: Dopants and Resistivity
High-quality wafers must also meet precise electrical specifications. Dopant type, concentration, and resistivity determine how the wafer behaves electrically and how well it supports device architectures for logic, RF, sensors, and photonics.
Consistent resistivity across the wafer and from lot to lot is essential for predictable device behavior and meaningful experimental comparisons.
Cleanliness and Contamination Control
Beyond visible cleanliness, wafer quality depends on tight control of impurities and surface particles. Oxygen and carbon levels within the crystal, as well as particle counts on the surface, are managed to prevent defect formation during high-temperature processing.
For advanced research and pilot production, low particle levels and controlled impurity content help protect yield and reduce unexplained process variation.
Why Quality Matters More in US-Based Research
In US laboratories and fabs, wafer quality directly affects development timelines and cost efficiency. With rising tool costs and tighter budgets, starting with well-specified wafers reduces the risk of failed runs and repeated experiments.
Understanding which specifications truly matter allows researchers and engineers to select wafers that align with their process goals without overpaying for specs that do not add value to a given application.
Flatness Metrics: Bow, Warp, and LTV
Flatness is not a single number but a set of related metrics that describe how a wafer deviates from an ideal plane. Bow refers to the overall curvature of the wafer, while warp captures the peak-to-valley deformation across the surface. Local Thickness Variation (LTV) focuses on smaller regions and is especially important for advanced lithography and bonding processes.
Tighter flatness specifications help maintain focus margins during exposure and reduce overlay errors, making them critical for advanced CMOS, photonics, and wafer-scale integration work.
Surface Roughness and Process Compatibility
Surface roughness directly influences thin-film quality, epitaxial growth, and optical losses. Ultra-smooth surfaces enable uniform film deposition and reduce scattering in photonic devices, while rougher surfaces can introduce defects or variability during processing.
For applications such as epitaxy, SOI bonding, and silicon photonics, surface roughness is often treated as a functional requirement rather than a cosmetic one.
Why Polish Type Impacts Yield
Polish choice affects more than appearance. Single-side polished wafers are suitable for many front-side processes, but double-side polished wafers provide improved symmetry and thickness control. This can be critical when both sides of the wafer interact with tooling, chucks, or bonding interfaces.
Processes that rely on tight mechanical alignment or double-sided processing often benefit from DSP substrates to reduce stress-induced distortion.
Electrical Uniformity Across the Wafer
In addition to nominal resistivity, electrical uniformity across the wafer surface plays a key role in device consistency. Variations from center to edge can lead to performance spread that looks like a process issue but originates at the substrate level.
For sensitive experiments and pilot production, tighter electrical uniformity supports more meaningful comparisons between dies and across wafer lots.
Scaling from R&D to Production
Many US labs begin development on small-diameter wafers before scaling to larger formats. Using consistent quality specifications such as flatness targets, polish type, and impurity control helps ensure that results obtained on 100 mm or 150 mm wafers translate reliably to 200 mm or 300 mm platforms.
Understanding which quality metrics scale cleanly allows teams to plan transitions without introducing unexpected variability or yield loss.
Balancing Specs and Cost
Not every application requires the tightest available tolerances. Selecting quality specifications that align with actual process needs helps control costs while still maintaining reliable performance.
By understanding which wafer specs directly impact your process, you can avoid over-specifying substrates and focus investment where it delivers real value.