Electron Beam Lithography Research

What Is Electron Beam Lithography

Electron Beam Lithography (EBL) is a high-resolution patterning technique used in micro- and nanofabrication. It uses a tightly focused beam of electrons (instead of light, as in photolithography) to directly write custom patterns onto a resist-coated substrate, such as a silicon wafer.

Key Characteristics:

• Resolution: Can achieve feature sizes down to a few nanometers.

• Flexibility: Ideal for research and prototyping since it does not require masks.

• Speed: Slower than optical lithography due to its serial writing process.

How It Works:

1. Substrate Preparation: A wafer (e.g., silicon) is coated with an electron-sensitive resist, like PMMA (polymethyl methacrylate).

2. Exposure: The electron beam scans across the surface and modifies the solubility of the resist in the exposed regions.

3. Development: The exposed (or unexposed, depending on resist type) areas are removed in a developer solution.

4. Pattern Transfer: The developed pattern can be etched or used for material deposition.

Substrates Used For The Following Applications

Here are the typical silicon wafer specifications used for each of the applications you listed:

1. Nanostructure Fabrication

• Diameter: 100 mm or 150 mm (small-scale research)

• Type: Prime-grade, float-zone (FZ) or Czochralski (CZ)

• Orientation: ⟨100⟩ or ⟨111⟩ depending on etching profile

• Doping: Undoped or lightly doped (n-type or p-type)

• Resistivity: High (>1,000 Ω·cm) for reduced background conductivity

• Surface: Double-side polished (DSP) for high-resolution lithography

2. Quantum Dot Arrays

• Diameter: 100 mm or smaller (e.g., 50.8 mm for test runs)

• Type: Undoped or intrinsic silicon

• Orientation: ⟨100⟩ for uniform electronic properties

• Resistivity: Very high (>10,000 Ω·cm)

• Surface: Atomically smooth DSP surface; epi-ready optional

• Note: SOI (Silicon-on-Insulator) wafers are often used for vertical confinement

3. Photonic Crystals

• Diameter: 100 mm or 150 mm

• Type: SOI wafers preferred (device layer: 200–300 nm typical)

• Orientation: ⟨100⟩

• Doping: Lightly doped or intrinsic

• Surface: DSP, with top layer optimized for etching photonic structures

• BOX Thickness: 1–3 μm buried oxide layer depending on design

4. Semiconductor Device Prototyping

• Diameter: 100 mm, 150 mm, or 200 mm

• Type: Prime-grade, CZ

• Orientation: ⟨100⟩ standard

• Doping: n-type or p-type (Boron or Phosphorus), depends on device

• Resistivity: 1–10 Ω·cm typical for CMOS/MOSFETs

• Surface: Single-side polished (SSP) or DSP for multilayer builds

5. MEMS and NEMS Development

• Diameter: 100 mm or 150 mm (lab use), 200 mm (industrial)

• Type: SOI wafers or thick DSP CZ wafers

• Orientation: ⟨100⟩ or ⟨110⟩ for anisotropic etching

• Doping: Lightly doped or intrinsic for mechanical stability

• Device Layer (SOI): 1–100 μm depending on structure thickness

• BOX Layer: 1–3 μm for MEMS release processes

• Handle Wafer: Thick for structural support (500+ μm)

Advantages:

• Ultra-high resolution

• No need for photomasks

• Ideal for low-volume, high-precision work

Limitations:

• Low throughput

• Expensive equipment

• Sensitive to vibration and contamination