100mm & 150mm Silicon Carbide Wafers 4h and 6h for High-Power Devices

University Wafer Silicon Wafers and Semicondcutor Substrates Services
University Silicon Wafer for Production

Get Your 100mm & 150mm SiC Wafer Quote FAST!

Our Silicon Carbide (SiC) wafers are used to fabricate High-Powerd Devices

Silicon Carbide (SiC) High crystal quality wafers for all your demanding power electronics. Silicon carbide (SiC) power device manufacturers demand the highest quality wafers to meet the performance and reliability required in advanced power electronics systems. 4H SiC Prime Grade wafers mean it's of the highest product quality and reliability that work great for research and production.

Why Use Silicon Carbide Substrates instead of Traditional Silicon Wafers?

Silicon Carbide (SiC) devices work better and more efficiently than silicon and other substrates when electonic devices need to handle high currents, high voltages and higher temperatures. SiC is the future of hybrid and electric vehicles, industrial applications, and generation and distribution of renewable power.

Why Buy Silicon Carbide Wafers from UniversityWafer?

There are many reason to purchase substrates from UniversityWafer, Inc. Below are just some of the reasons to buy SiC substrates from us.

  • Optimizes targeted performance, high ROI for your next generation power electronics devices
  • Highest quality SiC crystals
  • Lowest SiC defect densities

Silicon Carbide That Consistent, Reliable Quality

Our 100 mm SiC Wafers offer device researchers and manufacturers with consistent, high quality specification to help develop high-performance power devices. Our high quality SiC wafers wafers are produced from 4H, 4° off-axis, n+ SiC ingots manufactured using physical vapor transport (PVT) growth techniques as well as artificial intelligence. Advanced wafer production techniques are used
to convert silicon carbide ingots into SiC wafers thus ensuring a quality device that works consistantly and reliably.

What Silicon Carbide (SiC) Grades are Available?

This SiC substrate grading structure sets a higher standard for specifying tolerances. At the highest quality tier, materials feature defect densities as low as MPD <= 0.1 cm-2, TSD<= 500 cm-2 and BPD <=1,000 cm-2.
Prime Grade   offers three product tiers of 100 mm SiC substrates of increasingly tighter tolerances:

SiC Grades



Prime Std Guaranteed MPD tolerances. Balances performance and cost for electronic components with low to medium
current ratings.
Schottky and junction
barrier Schottky diodes
Prime Select More stringent tolerances for MPD current ratings and
TSD. Allows for manufacturing with mid-range current
Pin diodes and switches
Prime Ultra Extremely low MPD, TSD and BPD tolerances and
tightened wafer resistivity. Ensures product quality and
improves cost efficiency in manufacturing high current
High current and voltage MOSFETs, JFETs, IGBTs,
BJTs, and pin diodes with large die areas

Epi-Ready Silicon Carbide Wafers

We have a large selection of SiC substrates 4H and 6H epi ready. You can buy as few as one wafer in diameters ranging from 5mm x 5mm up to 150mm.

Many are in stock and ready to ship.Silicon Carbide Wafers

Silicon Carbide Grade Specifications

Specs Standard Select Ultra
Diameter (mm) 99.7 - 100
Thickness (um) 330 - 370
Primary Flat Length (mm) 31.50 - 34
Bow, um +/-20um
Warp, um <=30um
TTV, um <=5um
SBIR, um <=2um
Foreign polytypes, % 0
Visible scratches, mm <=15um
Resistivity, ohm-cm 0.014 - 0.024 0.015 - 0.023 0.016 - 0.022
Total usable area(1), % >=95 >= 98 >= 99
Dislocation density(2), cm-2      
EPD (mean) <=12,000 <= 10,000 <= 8,000
TED (mean) <= 9,000 <=8,000 <= 6,000
TSD (mean) <= 1,000 <= 800 <= 500
BPD (mean) <= 2,000 <= 1,500 <= 1,000
MPD, cm-2 <= 0.5 <= 0.2 <= 0.1

Total Silicon Carbide usable area calculation includes Candela CS20 measurements for surface defects and micropipes to determine an accurate percentage usable area calculation.” Inspection area on a 2 x 2 mm grid with 3 mm EE.

Dislocation density is determined by KOH etching using a 65-point radial measurement technique on 1 wafer per ingot.