SIMOX Silicon-on-Insulator for Research & Development

university wafer substrates

How to Make SIMOX SOI Wafers

In this (SIMOX) method, ion implantation is used to create a silicon dioxide layer on the wafer surface and to control the thickness of the upper silicon layer. This method may also involve the removal of a second silicon oxide film from the mask layer and the formation of a layer of silicon-on-silicon SOI.


200mm SOI Wafers in Stock

Device Layer (nm) Box Layer (nm) Handle Layer (um) TTV (um) Qty in Stock
55 145 725+/-15 <1 184
70 145 725+/-15 <1 253
70 2000 725+/-15 <1 1756
75 250 725+/-15 <1 18
80 1000 725+/-15 <1 374
88 200 725+/-15 <1 23
145 1000 725+/-15 <1 9166
160 400 725+/-15 <1 24
300 300 725+/-15 <1 43
400 150 725+/-15 <1 21
700 2000 725+/-15 <1 22
1250 145 725+/-15 <1 353
1250 400 725+/-15 <1 19
2100 400 725+/-15 <1 16
3500 400 725+/-15 <1 46
3000 300 725+/-15 <1 4414


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SIMOX Silicon-on-Insulator Wafers

Below are just some fo the thin device layer SOI that we sell online.

If you don't see a spec that you can use, please fill out the form for an immediate quote.

Item Dia Typ/Dop Ori Res ohm-cm Handle Device nm Oxide μm (or nm)
2327 25mm sq P/B (100) 14-22 625 500 3
2377 150mm P/B (100) 14-22 675 100 200nm
2415 150mm P/B (100) 13.5-22.5 625 500 3
2265 200mm P/B (100) 9-16 725 145 135
2266 200mm P/B (100) 9-16 725 190 150
2551 200mm P/B (100) 1-20 725 70 2,000nm
2268 300mm P/B (100) 9-16 775 50 145

How Are Simox Silicon-On-Insulator Made

IBM East Fishkill, NY, recently announced a partnership with IQE to manufacture mainstream microprocessors on silicon insulator wafers (SOI). For the first time in its history, IQe has increased the thickness of silicon on insulators. A thin layer of silicon is placed on the silicon dioxide (SiO2), also known as the buried oxide layer. This layer is used to manage the heat, heat dissipation and thermal conductivity of semiconductor materials such as silicon, copper, nickel or iron. [Sources: 3, 7, 8, 11]

The wafers are then subjected to conventional annealing using a vacuum chamber with high - temperature and low - pressure (low pressure), creating a buried oxide layer (BOX) that forms both the insulator (silicon) and the insulator (SOI). To form the wafer bond, a large part or the entire wafer is cut so that a thin SOO2 silicon film is placed on this oxidizing agent. The Annesal is a neutral environment, like nitrogen, so the silicon reacts with the insulator material and improves the quality of its layer on the surface of both substrates, creating a uniform, buried insulation layer. [Sources: 1, 9, 10]

In wafer production, the oxygen ions combine with the silicon atoms on the substrate to form silicon dioxide. The volume is increased by implanting an oxygen ion into the "oxygen implantation region" and by oxidising silicon by annealing treatment, creating the BOX layer. [Sources: 0, 5]

The wafer is subjected to conventional chemical vapor deposition (CVD) using silicon gases, resulting in silicon oxide (SOO 2) and silicon dioxide (SiO 3). It is deposited on the buried oxide-BOX layer, which forms an insulator and a silicon-on-silicon SOI (insulators). The result shows that a plasma source implantation of oxygen, followed by thermal annealing, forms a layer of buried Sio 2 with a surface area of about 1.5 micrometers. In contrast, the wafers are subject to the conventional annesaling process, in which chemical vapour is separated by means of chemical oxidation and oxidation by oxidation with oxygen and oxygen ions. This creates an oxide layer in which the silicon atoms are oxidized and deposited on the substrate, while silicon gases of both types are used in contrast to conventional chemical vapor deposition (CVD). It was deposited with conventional chemical vapour deposits (BVD). [Sources: 9, 10]

In this method, ion implantation is used to create a silicon dioxide layer on the wafer surface and to control the thickness of the upper silicon layer. This method may also involve the removal of a second silicon oxide film from the mask layer and the formation of a layer of silicon-on-silicon SOI. [Sources: 0, 5]

The market for silicon insulators is segmented by type, such as fully depleted, partially depleted silicon and fully depleted silicon. What we need is increased production of silicon-on-silicon SOI for the production of high-performance and low-power applications. It is also necessary to reduce the limits within which flat insulator layers can be formed within the silicon insulator structure. The market is divided by type: partially exhausted, completely exhausted, partially exhausted and fully exhausted silicon and other species. [Sources: 2, 9, 12]

asi - with substrategies - is also understood to be a patterned preformed silicon insulator that comprises individual and several buried oxide regions formed within it. This also includes patterned silicon-on-silicon (SOI) and silicon oxide (SOSO) substrates. The patterns include a single, multiple or buried oxide regions that form in it, as well as a flat insulation layer. [Sources: 4]

Silicon-on-insulator (SOI) refers to a substrate with a single, multiple or buried oxide region and a flat insulation layer. [Sources: 11]

The insulator is usually made of thermal silicon oxide (SiO2) and consists of a single layer of silicon oxide and a flat insulation layer. On a silicon wafer, the substrate is or has been embedded in the silicon wafer and almost invariably contains a thermal silicon oxide layer (SiO), or on a SOI wafer, or were the insulators in a thermal silicon oxide (Si O2) or in a SoI wafer. On a silicon-on-insulator (SOO), the substrates are (or were) on the silicon wafers and almost inevitably form a thermal, silicon oxide (SO) layer. [Sources: 2, 6, 12]

The silicon layer can be up to ten micrometers thick, but depending on the application it can also be very thin (50 nm) until the transistor is completely exhausted, and it varies depending on the application. The silicon layers can be either tens of micrometers thick - or not, depending on the application, they can only be as thin as 50 nm, with a completely exhausted transistor, or as thick as 100 nm, in a silicon-to-insulator (SOO) wafer. In the case of a single layer of thermal silicon oxide (SiO2), the silicon layer can often be 10-20 micrometers thick and even very thin 50 nanometers, in some cases it can be so thin that it does not even need to be completely used up for a transistor. It can be ten micrograms thick, or more than ten micrograms - centimetres thick. [Sources: 5, 6]