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We use them for etching with DRIE some precursors as part of the fabrication of X-ray micro-lenses.
Si Item# 1116 Silicon
100mm P/B <100> 10-20 ohm-cm 500um SSP
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Scientists have used the following wafers for their research.
Silicon 150mm P /B <100> 0-10 620um SSP
Reactive ion etching Topography (RIE) is considered one of the most promising applications of deep reactive ion etching (DRI) technology and has developed a new method to predict and find the right chemical composition for a wide range of applications in the MEMS industry. In addition to the Bosch process of silicon etching in MEMs, this new approach to reactive ion etching can also be suitable for production in other applications. [Sources: 0, 4, 6]
The manufactured silicon part is extremely well defined and the final etching depth is controlled at 2% of the target depth. The final etching depth can be controlled with the help of a high-resolution 3D laser with a depth target of 1.5 mm. [Sources: 1]
During the etching process, the passivation layer of the silicon side wall is exposed and quickly consumed. DRIE etchings are started with a patterned mask and the first pattern is etched in silicon. After the SiO 2 step is defined, we can begin etching on silicon with the help of a high-resolution 3D laser with a depth target of 1.5 mm. SIO 2 is predefined, and we start at the deepest caustic depth and repeat it until the end of the layer. [Sources: 1, 3]
Another problem is that the etching selectivity of photoresist lacquers on silicon is not always sufficient to etch the entire thickness of the wafer. This means that it takes longer to remove the F atoms from the passivation layer, and finally they can be etched into the silicon passivation layer. [Sources: 1, 3]
This is bad for achieving the ideal etch rate, as excessively high flow rates are not good for the etch rate and sidewall quality. High-pressure etching during this time usually leads to a higher flow rate than the normal etching rate of photoresist lacquers on silicon. This may be due to the acidic movements that form on the silicon passivation layer, as well as the presence of acidic ions in the wafer. [Sources: 0, 3]
DRIE glass requires high plasma cable performance, making it difficult to find a high-pressure etching solution with high flow rate and side wall quality for the glass. [Sources: 8]
This allows the plasmas to reach the ground during the etching cycle and a smooth side wall can be achieved. As the trench widens, more polymer material is deposited and slows the etching rate, resulting in an etching rate of 25 W exceeding 35 W if the width of the trenches is greater than 15 W. Increased physical and chemical reactions, such as chemical reactions, etch silicon combs faster than sinks in the side walls. Sputtering polymer materials are also washed back into the surface at deeper points, creating a much thicker polymer film and slowing the etching rate. [Sources: 2, 3]
Under experimental conditions, we found that the best etching pressure is 30 mTorr, which gives a rate of 25 W per square centimetre of silicon honeycomb per second. It seems that we can achieve a high level of etchability at low temperature and pressure of 30 - 35 m Torr. [Sources: 3]
By using the isotropic etching of chemical mixtures, in which the etching rate decreases from the needle tip to the Base50, sharpening can be achieved much faster. In the pulsed etching system presented in this paper, we recorded the highest instantaneous etching rate of silicon at an initial pressure of 1 xef2, which is at an initial pressure of -1 xEF2. [Sources: 0, 5]
The energetic ions during the ON period bombard the strongly chlorinated silicon surface, resulting in an unusually high etching yield. However, under high pressure conditions, the chemical mixtures with high ion concentrations and high surface area are not embedded at the same speed. [Sources: 0, 3]
When the depth in the trench 25 - 110% wide approaches 70%, the etching stops at 50 mTorr pressure because the energy of the ion flux is too low to reach it. Figure 3: If the trench is narrow and the preload is high (the polymer material is largely deposited back along the side wall and does not affect the reactive plasma etched into the bottom of silicon), the etching rate is higher. Compared to the biases, it seems that the pressure inside the etching chamber affects the profile of etched structures in a more complex way. ICP pulse mode, in which the ion energies are high they report an etching rate of up to 40%, which means that individual ion impacts on the surface produce an acratera of 2anm depth. [Sources: 0, 3]
There are a number of settings that influence the etching reaction, including the depth of the trench, the preload and chamber pressure, and temperature and humidity. The pressure of the chamber is generally determined by pressure on the surface, temperature, humidity and other factors such as temperature. [Sources: 3, 7]
It can be said that no single processing step has done more to enable MEMs than deep reactive ion etching (DRIE). Managing is associative Is an essential MEMS manufacturing process and technology that enables high aspect ratio microstructures. [Sources: 4, 7]