UniversityWafer, Inc. has been mentioned over 19,000 times below are just a small selection our mentions with our wafers. Send us your specs and we'll quote you! Below are just some snippets!
To perform the present experiments, 5 nm of titanium(adhesive layer) and 150 nm of nickel were evaporated on silicon wafers with 300 nm of thermal oxide (University Wafer,Inc., U.S.A.). A small beaker with a dened area of 0.78 cm2 wassealed on the nickel surface. Both wild-type and D96N bR wereprepared in a carbonate buffer (5μM in 50 mM sodiumcarbonate buffer). Different amounts of wild-type and D96N bR were physisorbed on the surface using the drop-castingmethod and left to dry in vacuum for 48 h.
Partialdehydration was accomplished by using 20% EtOH 15 min,40% EtOH 15 min, 50% EtOH 15 min, 70% EtOH 15 min, 85%EtOH 10 min, followed by 1 h in a 2:1 LR White to 85% EtOH.Sections of LR White embedded samples were cut on a Leica UC7Ultramicrotome using a diamond knie. 200 nm and 400 nmsections were picked up with a perfect loop, placed on top of a polished silicon (Si) wafer (Catalog #534, University Wafer Inc.,South Boston, MA, USA), and let air dry on a 35°C hot plate.
As shown in Supplementary Fig. 1, the nanomesh patterning started with a silicon-on-insulator (SOI) wafer which was commercially available (SIMOX SOI, distributed by University Wafer). The SOI wafer consisted of a top Si layer that was a single-crystalline Si with (100) crystal orientation, lightly p-type doped with a doping concentration of 1 × 1014 cm−3 and a thickness of 145 nm. The buried oxide layer was 120 nm thick, and the handle wafer was 750 μm thick.
Procedures by chip design The following sections briefly outline the procedures which were used for each style of chip; refer to section A.1 on page 102 for detailed instructions for each individual process. All wafers used were 300 µm thick {100} Si, lightly p-doped (with B) to a resistivity of 1 − 10 Ωcm. The wafers were 4” in diameter, polished on both sides, and were purchased from University Wafer. When describing wafer orientation, the “window” side refers to what will be the interior of the fluidic cell, with an intact Si3N4 membrane.
For wet etching, borosilicate glass (Borofloat 33 from UniversityWafer, Inc, 500 μm thick) and fused silica glass (UniversityWafer,isotropic, even with lower HF concentration.
3-Inch-diameter silicon wafer (University Wafer, cat. no. 1196) 3-Inch-diameter glass wafer (University Wafer, cat. no. 1610)
...t. Fig. 2.2.2: IR absorbance spectra of Li-OH and Li-OD complexes in (a) H- and (b) D- treated ZnO (University Wafer). The isotopic substitutions of hydrogen ( 1 H and 2 H), oxygen ( 16 O, 17 O, and 18 O),
North American. 3 inch Si wafer with 300 nm wet thermal oxide (Si/SiO 2 wafer) was purchased from University Wafer. 6.3.2. Few-Layer Graphene Growth FLG electrodes were grown using a modified atmosphere pressure ch...
Silicon wafers (2-inch diameter, Type-P, 1S polished; University Wafer, cat. no. 0.75 mm diameter, Harris Uni-Core) /32'' OD PTFE microtubing (Cole Parmer, PTFE#30).
abricated from a 100 nm thick stoichiometric Silicon Nitride film on a 500 μm Silicon substrate (University Wafer). First, the metallization of the actuation and read-out electrodes along with the contact pads was...
Wafers (Silicon <100> P/Boron, >5000 ohm-cm, double side polish, <10 Angstrom Ra) were received from University Wafer (Boston, MA). NMP) was exfoliated by ultrasonic dispersion using a SYCLON ultrasonic cell crusher
laser ionization/deposition (MALDI):hASCs were grown on indium tin oxide (ITO) coated slides (UniversityWafer Inc, MA, USA). All chemicals for matrix preparation such as methanol, LC-MS grade water, and DHB
...Preparation of Silane Monolayers. Single side polished GaAs(100) substrates (AXT, 400 μm, Si-doped, University Wafer, Inc., Boston, MA) were etched and cleaned following the procedures described previously by Jun et ...
...by reactive ion etching (RIE) the exposed oxide and Si substrate. Fabrication on a glass substrate (University Wafer) has the advantage of reducing the parasitic capacitance and allowing for high-resolution imaging