Silicon Wafers for NMOS Device Fabrication

Compare p-type, undoped and SOI silicon substrates for NMOS fabrication research. Select wafer doping, orientation, resistivity and finish to match your device process.

UW Logo

Choosing Silicon Wafers for NMOS Research

For a conventional enhancement-mode NMOS transistor, fabrication typically starts with a p-type silicon substrate or p-well. The process forms n-type source and drain regions on either side of a gate dielectric and gate electrode. The appropriate wafer resistivity and substrate doping depend on the device design and process flow.

UniversityWafer can quote p-type silicon wafers with your required diameter, (100) orientation, resistivity, thickness, surface finish and quantity. If your research uses a different starting material, specify the planned well implants, body contact and isolation steps.

Undoped Wafer Option for Process-Specific Research

Silicon item #3193 is listed as a 100 mm, undoped, (100), >10,000 Ω·cm, approximately 525 µm, double-side-polished (DSP) wafer. It can serve projects that specifically require a high-resistivity, undoped starting substrate. It is not a drop-in replacement for a p-type NMOS starting wafer: confirm the intended doping or well-formation steps with your fabrication team. Ask us to verify current stock, TTV and any additional tolerances before ordering.

Illustration of an NMOS transistor with gate, gate dielectric, source and drain on a silicon substrate

Get Your NMOS Silicon Wafer Quote FAST! Include the device architecture, conductivity type, orientation, resistivity, diameter, thickness, polish and quantity. Or, view undoped research item #3193 online.





Silicon Substrates for NMOS Device Fabrication

An NMOS (n-channel metal-oxide-semiconductor) transistor uses a gate voltage to create an electron-conducting channel between n-type source and drain regions. In a conventional bulk-silicon design, the channel forms at the surface of a p-type body beneath the gate dielectric. Selecting the wafer begins with the body doping, electrical targets and fabrication steps.

Silicon wafer applications in NMOS transistors, CMOS circuits, and device test structures

Specifications to Include in Your Wafer Request

  • Conductivity and resistivity: p-type boron-doped silicon is a common starting point for bulk NMOS; choose its resistivity to match the process design.
  • Orientation: (100) silicon is commonly used for MOS fabrication. Specify your required cut and tolerance.
  • Diameter, thickness and finish: match the wafer to the tools and handling process; request SSP or DSP and a TTV limit where needed.
  • Surface and layers: define cleaning, gate-dielectric growth or deposition, and any pre-existing oxide or epitaxial layer separately.

How an NMOS Device Is Fabricated

A research flow may include wafer cleaning, isolation, gate-dielectric formation, gate patterning, source/drain doping, annealing, contact formation and interconnect deposition. Exact order and materials vary by device architecture. The wafer's polish and cleanliness help subsequent lithography and film processing, while the starting doping and later implants set electrical behavior.

Bulk Silicon, Undoped Silicon or SOI?

Choose a p-type silicon wafer for many conventional bulk NMOS processes. An undoped, high-resistivity wafer may fit specialized research if the required p-type body is formed as part of the process. A silicon-on-insulator (SOI) wafer has a silicon device layer separated from the handle wafer by buried oxide; its device layer doping and thickness must also suit the transistor design. These are distinct starting platforms rather than interchangeable specifications.

Related NMOS and Silicon Wafer Resources