Thermal Oxide Leakage Wet vs Dry

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Thermal Oxide Leakage Question

FAQ

Q. Hows the leakage issue of the thermal oxides?

A. Wet thermal oxide isn’t really designed for insulation/isolation.  It is great for photolithography masking, but is too porous to make a good insulator.  At 300nm it may work if the conditions are not too extreme.  Our recommendation for isolation oxides or gate oxides is Dry Thermal Oxide, especially Dry Thermal Chlorinated Oxide.  300nm of this should take care of leakage.  There is the top of the line oxide, Dry Thermal Chlorinated Oxide with an anneal in forming gas, but this isn’t usually needed.

Summary – 300nm of wet oxide may be fine, but it is better to go with 300nm of dry oxide and maybe one of the upgrades.

 We don’t have any data on leakage or breakdown voltage.  This depends too much on the customer’s processing and on their test method.

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What is Thermal Oxide Leakage?

In microfabrication, thermal oxidation is one of the ways to produce powerful, cost-effective and environmentally friendly silicon wafers on the surface of a wafer. Improving the performance of tetraethylorthosilicate (TEOS), which is used as a silicon source, is a well-known technique for the precipitation of a large amount of thermal oxidizing agent (TOS) in the form of silicon oxide. [Sources: 2, 10]

The oxidant H 2 O penetrates into the thermal oxide layer [18], which is thermally cultivated by wet oxidation. The surface of the wafer is oxidized and forms a gate-oxide layer in which gate-oxide layers for integrated circuits are formed [19]. [Sources: 1, 6]

The surface of the semiconductor substrate must be extremely clean to reduce the oxide leakage current. The growth rate of the oxides is very fast, but slows down as oxygen diffuses through the silicon substrate before it reaches it. As soon as the EOT of the silicon oxide layer drops below about 20 angstroms, it becomes imperative to reduce the leakage current of the oxides [19]. [Sources: 0, 6, 11]

Furthermore, the skilled workers will appreciate that the rapid thermal oxidation process described above is exemplary and that various parameters for rapid thermal oxidation can be used to form the silicon oxide layer [42]. The chemical oxide layers protect the silicon surface from roughening after high-temperature oxidation and the final SPM cleaning is formed on the silicon surface. [Sources: 6, 11]

In addition, PECVD deposited SiO (x) films exhibit more defects and states, including hanging bonds in the thermally grown films, compared to quartz. The thickness of the field oxide layer can be several micrometers, and the thickness of oxide capacitors and dielectric is as thin as several angst currents. This means that even in thick thermal oxides, there is an ashlard tone of a few atomic layers. In addition, thermal oxidation leads to more defects (including dangling bonds) in thermally grown Si O (X) films compared to quartz, and to more than twice as many atoms in thermally grown SiO [x] films. [Sources: 3, 7, 9]

One method of reducing leakage is to include nitrogen in the nitridation process used in silicon oxide layers to form silicon oxide nitride (SiON) layers. The two-stage nitrogen enrichment process increases the dielectric constant of toroxides by a significant amount, reduces their effective thickness in relation to the gate capacity and reduces the leakage current by increasing the number of atoms in their oxide layer. By reducing the effective oxide thickness, the performance of the MOSFET formed from the peat oxide can be improved by making the oxide more resistant to leakage currents and thermal oxidation by nitritation. [Sources: 4, 11]

This has been demonstrated in several tests comparing the performance of the ISSG - cultivated oxide and the oxide grown in an oven. Further experiments have also shown that both the oxides grown at the ISSg and the dried, fast thermal oxidation (RTO) produced by nitritation of peat oxide in an oxygen-free environment at high temperature and pressure are less likely to escape. ISSG oxide has consistently shown significantly lower leakage rates in terms of both gate capacity and leakage current than the oxidised, dry-dried oxidising agent from the furnace. [Sources: 8]

This is in line with the results of the PECVD - deposited thermal oxidation (Fig. S4 and S5), in which the thermal oxidized Si plate and the dry dried oxidising agent produced the same foil for thermal oxidation from the furnace. To further investigate the effects of thermal oxidation on the leakage rate and leakage current of Si plates, we investigated the performance of both ISSG - Cultured Oxides and RTO - Dry Oxidized Thermo Oxides in the presence and absence of oxygen at different temperatures and pressures. [Sources: 3, 5]

The refractive index as measured by ellipsometry is very close to that of thermal oxides, which means that the refractive index of silicon oxide films is closer to the stoichiometric composition than that of the thermal oxide film (Fig. S5). Silicon oxides, however, have always been closely linked to stoichiometry, whereas according to our observations, thermal oxide films have not. [Sources: 2]

The high d values indicate the presence of thermal oxidation in the silicon oxide films and the presence of stacking defects. Thermal oxidation can also cause stacked defects on the substrate, which are structural defects in a silicon lattice. Stacking defects occur when excess silicon atoms accumulate on a substrate due to oxidation, which leads to dislocation of silicon atom lattices (Fig. S5). [Sources: 0, 7]

Note that the offset of the conductor tape that determines the thickness of the door - oxide layer and its thickness depends on the orientation of the substrate and the thickness of the oxide. Fewer and fewer gate oxides can penetrate the underlying silicon due to their thickness (Fig. S5). [Sources: 4, 7]

Equivalent oxide thickness (EOT) is the number used to compare the thickness of an MOS transistor with a dielectric layer of silicon dioxide gate with the thickness of a dielectric transistor with a higher LECTric constant. The Eot is a measure of the amount of silicon dioxide gateoxides required to obtain the same thickness as an M OS transistor with a high dialection layer. E OT corresponds to the total number of silicon oxide crease oxide layers that have to be extracted for the Mos transistor with the highest -k The electron oxide layer (Fig. [Sources: 11]

Sources:

[0]: https://virginiasemi.wordpress.com/2017/06/01/thermal-oxidation-for-silicon-wafers/

[1]: https://www.google.si/patents/US5972753

[2]: https://www.scielo.br/scielo.php?script=sci_arttext&pid=S0103-97332001000200023

[3]: https://www.nature.com/articles/s41598-018-32233-4

[4]: https://patents.google.com/patent/US6362085

[5]: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6479920/

[6]: https://patents.justia.com/patent/6232241

[7]: https://www.intechopen.com/books/physics-and-technology-of-silicon-carbide-devices/fundamental-aspects-of-silicon-carbide-oxidation

[8]: https://link.gale.com/apps/doc/A63975473/AONE?u=googlescholar&sid=zotero&xid=bd91962f

[9]: https://link.springer.com/10.1007/978-3-642-27758-0_1173-2

[10]: https://en.wikipedia.org/wiki/Thermal_oxidation

[11]: https://www.google.com/patents/US7928020