Double Side Polished Silicon Wafers
Double Side Polished (DSP) Silicon Wafers
We have a large selection of ultra-flat double side polished prime grade and test grade silicon wafers in all diameters, thickness, Ori and resistivities. We have Total Thickness Variations as tight as 1 micron TTV in stock.
In order to increase the flatness of a silicon wafer is to polish the back-side of the wafer. The double side polishiing helps reduce the roughness of the silicon wafer surfaces. This is a must when making MEMS devices where super flat and low roughness specs are required.
Below are just some of the double side polished wafers with the tightest TTV.
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Gettering and Double Side Polished Silicon Wafers
It is interesting to note that borosilicate (BSG) and phosphosilicate (PSG) glass when contacting heated silicon are very good at removing a silicon wafer's deep impurities.
Double Side Polishing a must fror ultra-thin-silicon wafers.
We can make single side polished silicon wafers to 50 micron with tight TTV, but thinner than this requires the more expensive back side polishing to keep the wafers from warping.
Use double side polished silicon wafers when you need tighter TTV, BOW and WARP tolerances.
Material - CZ unless noted |
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| Item | Type/Dop | Ori. | Dia(mm) | Thk(μm) | Polish | Res Ωcm | Notes |
| 6971 | n-type Si:P | [100--25° towards[110]] ±1° | 6" | 675 | DSP | 1--100 | SEMI notch Prime, Empak cst, TTV<1μm |
| S5594 | P/B | [100] | 5" | 990 ±8 | DSP | 1--25 | SEMI Prime, Empak cst, TTV<1μm |
| D868 | P/B | [100] | 5" | 590 | DSP | 1--30 | SEMI Prime with Notch, TTV<1μm, Bow/Warp<10μm, Empak cst |
| F709 | n-type Si:P | [100] | 5" | 762 ±12 | DSP | 5--35 | SEMI Prime, 1Flat, Empak cst, TTV<1μm, Bow<5μm, Warp<10μm |
| S6284 | n-type Si:P | [100] ±1° | 4" | 200 ±10 | DSP | FZ >1,000 | SEMI Prime, 1Flat, TTV<1μm, in Empak cst |
| G706 | Intrinsic Si:- | [100] | 4" | 500 | DSP | FZ >20,000 | SEMI Prime, 1Flat, TTV<1μm, Empak cst |
| 6356 | Intrinsic Si:- | [100] | 4" | 500 | DSP | FZ >20,000 | SEMI Prime, 1Flat, TTV<1μm, Empak cst |
| J302 | P/B | [100] | 4" | 600 | DSP | 1--50 | SEMI Prime, 1Flat, TTV<μm, Empak cst |
| 7089 | P/B | [100] | 4" | 381 ±7 | DSP | 0.014--0.021 | Prime, 2Flats, Empak cst, TTV<1μm |
| F022 | P/B | [111] ±0.3° | 4" | 350 ±5 | DSP | <0.05 | SEMI Prime, 1Flat, Empak cst, TTV<1μm, Bow/Wrp<15μm |
| 6570 | n-type Si:P | [100] | 4" | 400 | DSP | 1--10 | SEMI Prime, 2Flats, TTV<1μm, With lasermark, Empak cst |
| 4975 | n-type Si:Sb | [211] ±0.5° | 4" | 1,500 ±15 | DSP | 0.01--0.02 | SEMI Prime, 1Flat, Empak cst, TTV<1μm |
| S962 | Intrinsic Si:- | [100] | 4" | 525 | DSP | FZ >20,000 | SEMI Prime, 1Flat, Super Low TTV<0.3μm over entire wafer, Empak cst |
| D796 | P/B | [100] | 4" | 500 | DSP | 1--30 | SEMI Prime, 1Flat, Empak cst, TTV<1μm |
| L302 | P/B | [100] | 4" | 625 | DSP | 1--50 | SEMI Prime, 1Flat,TTV<1μm, Empak cst |
| Q787 | P/B | [111] ±0.5° | 4" | 350 | DSP | 0.001--0.005 | SEMI Prime, 1Flat, Empak cst, TTV<1μm |
| J066 | n-type Si:P | [100] | 4" | 500 | DSP | 1--100 | SEMI Prime, 2Flats, TTV<1μm, With Lasermark, Empak cst |
| 4154 | P/B | [110] ±0.5° | 3" | 360 | DSP | 1--10 | SEMI Prime, 2Flats, TTV<1μm, 1--2 weeks ARO o repolish |
| 6826 | P/B | [100] | 3" | 475 | DSP | 1--50 | SEMI Prime, 2Flats, Empak cst, TTV<0.3μm |
| D750 | P/B | [100] | 3" | 420 | DSP | <1 | SEMI Prime, 2Flats, Empak cst, TTV<1μm |
| S5580 | n-type Si:P | [100] ±1° | 3" | 2,286 ±13 | DSP | 15--28 | SEMI Prime, 1Flat, TTV<1μm, Sealed in individual csts, in groups of 5 wafers |
| S5824 | n-type Si:P | [100] ±1° | 3" | 300 ±10 | DSP | 5--15 | SEMI Prime, TTV<1μm, Empak cst |
| 6400 | n-type Si:P | [100] | 3" | 350 | DSP | 1--25 | SEMI Prime, 1Flat, TTV<1μm, Empak cst |
| 6818 | n-type Si:P | [100] | 3" | 381 | DSP | 1--30 | SEMI Prime, 2Flats, Empak cst, TTV<1μm |
| H988 | P/B | [100] | 3" | 580 | DSP | 1--100 | SEMI Prime, 1Flat, TTV<1μm, Lasermark, Empak cst |