Indium Gallium Arsenide (InGaAs) Wafers for Research

university wafer substrates

Helping Researching Fabricate RC Detectors Using InGaAs

A semiconductor researcher requested a quote for the following:

Dear University Wafers team, I hope this email finds you well. I am writing to inquire about your capabilities in providing high Indium content (80-85%) InGaAs wafers for our detector fabrication requirements. We are currently seeking suppliers for these wafers as we aim to work with p-i-n photodiodes with tuning pixels for our sensing applications. Could you please provide us with information regarding the following: - Standard size or dimensions of the wafers. -Pricing structure for purchasing these wafers in bulk quantities. I plan on sharing the stack we are currently using (thickness, doping concetration) of InGaAs on InP depending on your reply. Additionally, if you offer customization options such as material for buffer layer or have specific technical specifications for your extended InGaAs wafers, we would appreciate receiving those details as well. Thank you for considering my request. I look forward to hearing back from you with the requested information at your earliest convenience.

Reference #295539 for specs and pricing.

Indium Gallium Arsenide Wafers In Stock

InGaAs is a high-mobility semiconductor that promises to increase a transistor's performance for high-frequency applications.

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Indium Gallium Arsenide Applications

Indium gallium arsenide (InGaAs) is a material that is often used in the production of semiconductor devices. It has a number of advantageous properties that make it useful in a variety of applications, including:

  1. Photodetectors: InGaAs is highly sensitive to certain wavelengths of light, making it an ideal material for use in photodetectors. It is often used in applications such as fiber optic communication systems and infrared cameras.

  2. Solar cells: InGaAs is also used in the production of solar cells, particularly in concentrator photovoltaic systems that use lenses to focus sunlight onto a small area of photovoltaic material.

  3. High-speed electronics: InGaAs has a high electron mobility, making it useful in the production of high-speed electronic devices such as transistors and integrated circuits. It is often used in applications that require high-frequency operation, such as in radar systems and high-speed data transmission.

  4. Medical imaging: InGaAs is used in the production of medical imaging devices such as CT scanners and PET scanners, which use radiation to create images of the inside of the body.

  5. Military and aerospace: InGaAs is also used in a variety of military and aerospace applications, including in the production of sensors and electronics for use in aircraft and missiles.

Overall, the main advantage of InGaAs is its ability to operate at high speeds and in a wide range of wavelengths, making it useful in a variety of applications that require these capabilities.


Commonly used to measure optical power in the near IR (NIR) range.

Indium Gallium Arsenide Photodetector


Indium Gallium Arsenide Transistor

We sell the InGaAs and InP Substrates. One concern with growing InGaAs on silicon is lattice mismatch. Our engineers may be able to help yu in this regard. Please email us today.

InGaAs for Thermophotovoltaic Application

A researchers asked the following:

I would like to order 2 wafers of InGaAs epifilm with complete structure as shown: ingaas.png Kindly note that this is a full structure all grown on an InP substrate. I would need the following information from you:

  1. The quote for the proposed structure
  2. Delivery time
  3. Method of payment
  4. What is the test of quality?

UniversityWafer, Inc. quoted and the researcher purchased:

$Contact Us, based on 2pcs. Reference RFQ#262172

1/ P-InGaAs or p-InP is doped by Mg or Zn, rather than Be.
2/ substrate is 350um.

What is Indium Gallium Arsenide (InGaAs)?

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Indium Gallium Arsenide (InGaAs) to Fabricate PN Junction Diode

I was wondering if you had InGaAs wafers. (In:Ga ratio 53:47) I need thick layers for my application, so the thickness needs to be thicker than 50 microns. Also, would it be possible to know which materials are available as wafers? (several hundred microns thick) I am looking for thick semiconducting materials for a detector application, but I want to also base my material choice on its availability. Please let me know.

It would be great if you could recommend to me the material, after I explain what the purpose of my device is. I am trying to create a structure like the image below:

InGaAs pn Junction Diode

It is a pn junction diode, which I plan to operate under reverse bias.
This is to create and collect charges as charged particles travel through the depletion zone. (My device is a particle detector)

fabricating pn-junction diodes

A university researcher asked the following:

I am wondering if the parts marked in red could be purchased from University wafer.
The material needs to be an n-type, with a window of p-type implant on the top surface.
I am planning to deposit metal on both top and bottom for electrodes, so it would be nice if the bottom layer has a material suitable for forming ohmic contact with metals. (the electrodes will probably be Cu/Au or Ti/Au).

The thickness of the bulk layer should be hundreds of microns, which I think is achievable with wafers.
Can you give me a list of wafers from the inventory which this setup would be possible?
After that, I can pick a suitable wafer from the list.

UniversityWafer, Inc. Quoted Replied:

I am not aware of any facility that grows bulk crystals of In(0.53)Ga(0.47)As alloy from which one could make wafers 50, or 100, or 350µm thick.

On the other hand, it is common to grow an Epi layer or layers of In(0.53)Ga(0.47)As on InP wafers (since the lattices match).
It is entirely common to grow a Zn doped p-type InGaAs on top of a Si doped n-type InGaAs layer.
However, in most such cases, the total InGaAs layer is about 1µm thick.

In theory, it is possible to grow a 40µm thick layer of InGaAs on an InP substrate. However, most such growth is done by the MOCVD process and this process gets very expensive for very thick InGaAs layers. However, if your budget can support it then we can make such wafers for you.

A characteristic of the MOCVD process is that it allows one to create very sharp transitions between n-type and p-type regions.

We shall try to offer the following:

Item Qty. Description
HD68. 2/10 Epi wafers, 2"Ø×350±25µm
Substrate: SI InP:Fe[100]±0.5°, Ro > 1E7 Ohmcm,
One-side-polished, back-side Alkaline etched,
Epi Layer 1: 40µm thinck, n-type In(0.53)Ga(0.47)As layer, Si doped, Nc=1E17/cc,
Epi Layer 2: 0.5µm thick, p-type In(0.53)Ga(0.47)As layer, Zn doped, Nc=1E18/cc
We are working on this RFQ, we should have a quote in a few days.

Please verify that this is what you need. We can offer double-side polished substrates and possibly substrates doped differently. We can offer different levels of doping and different thicknesses of the p-type layer.

I shall try to give you an idea of the incremental cost of the InGaAs layer thickness.

InGaAs Research Questions

A research client from a large semiconductor equipment manufacturer was interested in our InGaAs wafers.

Can you give me quotes on the 2" InGaAs wafers for the items below? 1. bare wafers, qty=10 to 100 2. Epi: Lattice matched n-type InGaAs:Si[100]±0.5°, thickness: 1.0um(±20%), Nc=1E17/cc, qty=10 to 100 3. InP/InGaAs/InP Epi wafers, qty=10 to 100

UniversityWafer, Inc. asked the following Questions.

You want me to quote the three structures shown in the image below? Material Stack. Is that correct?

Regarding (1)
a. Semi-Insulating InP - that is to be 2"Ø InP:Fe(100) substrate wafer and it is to be 400µm {not 400nm} thick. Is that correct?
b. 150nm InP layer - that is to be n-type InP:Si, Nc=(3-8)E18/cc. Is that correct ?
c. 850nm InGaAs layer - that is undoped, lattice matched In(0.53)Ga(0.47)As - Is that correct ?
d. 160nm GaAsSb layer - that is p-type (Zn doped), lattice matched GaAs(0.51)Sb(0.49):Zn - is that correct?
Nc=2E10/cc is unrealistic, if you want p+ then perhaps (3-8)E18/cc or even (1-3)E19/cc is reasonable - please decide

Regarding (2)
a. Semi-Insulating InP - that is to be 2"Ø InP:Fe(100) substrate wafer and it is to be 400µm {not 400nm} thick. Is that correct?
b. 150nm InP layer - that is to be n-type InP:Si, Nc=(3-8)E18/cc. Is that correct ?
c. 2,000nm InGaAs layer - that is undoped, lattice matched In(0.53)Ga(0.47)As - Is that correct ?
d. 160nm GaAsSb layer - that is p-type (Zn doped), lattice matched GaAs(0.51)Sb(0.49):Zn - is that correct?
Nc=2E10/cc is unrealistic, if you want p+ then perhaps (3-8)E18/cc or even (1-3)E19/cc is reasonable - please decide

Regarding (3)
a. Is the substrate to be 2"Ø Semi-Insulating GaAs:-(100), 400µm thick ?
b. The three layers, 1,600nm, 300nm and 100nm are these all undoped GaAs or should they be doped to different degrees?
What do you mean by HT
c. 10× - that is to be 10 layers of In(0.16)Ga(0.84)As, 12nm thick, interspersed with 0 layers of GaAs, 12nm thick - is that correct?
Are these to be undoped or doped to be p-type ? Do specify target Nc.
d. The 400 nm GaAs spacer - is that to be undoped ?
e. 10×- that is to be 10 layers of In(0.16)Ga(0.84)As, 12nm thick, interspersed with 0 layers of GaAs, 12nm thick - is that correct?
Are these to be undoped or doped to be n-type ? Do specify target Nc.
f. 750 nm n+ GaAs - is that to be GaAs:Si, Nc=(3-8)E18/cc ?

ingaas wafer

Please answer above to clarify what is needed.

Are you asking us to quote to make structures that you already use, or is this an experimental project/ If it is experimental then perhaps 1 wafer would be a better quantity to start with.

Do you actually need above structures or are you trying to get budgetary estimates. If these are budgetary estimates then I can give you an overall cost structure and you would not have to detail each request {for example, within broad limits the type and degree of doping has no influence on cost}.

We do want to help you any way that we can.

For your item 1:

What do you mean by "bare InGaAs" wafer?
Do you mean bulk InGaAs wafers, say 400µm thick?
What In:Ga ratio do you require?, Is it In(0.53)Ga(0.47)As or some other In;Ga ratio?
Are the wafers to be one-side-polished or double-side-polished ?

For your item 2:
What is the Epi-layer thickness? what is the Epi-layer doping?
The substrate InP wafer, is it to be Semi-Insulating or n-type Semi-Conducting?
Here is an example of such a wafer:

Item Qty. Description
GD16. 2/3/10 InGaAs:Si on InP:Fe Epi wafers,
Substrate: P/P 2"Ø×350±25µm InP:Fe[100]±0.5°, Ro>1E7 Ohmcm, EPD<1E4/cm²,
Both-sides-polished, EJ Flats (two),
EPI Layer: 0.75±0.15µm thick, n-type Lattice matched In(0.53)Ga(0.47)As:Si, Nc>2E18/cc
Note: Epi layer roughness close to one molecular layer; Some backside deposits expected.
Sealed in single wafer cassettes
Price: Depends on Qauntitiy

For your item 3
What is the IP Epi-layer thickness? what is the Epi-layer doping?
What is the InGaAs Epi-layer thickness? what is the Epi-layer doping?
The substrate InP wafer, is it to be Semi-Insulating or n-type Semi-Conducting?

Current InGaAs Inventory - Buy Online!

50.8mm Undoped (100) 350um SSP

Epi: Lattice matched n-type InGaAs:Si[100]±0.5°, thickness: 1.0um(±20%), Nc=1E17 -1E18/cc.

Sealed in individual wafer container. Substrate: 2" Indium Phosphide wafers, P/E 2"Ø×350±25µm.

 Epi: Lattice matched p-type InGaAs:Zn[100]±0.5°, thickness: 1.0um(±20%),Nc=1E17 -1E18/cc.

Sealed in individual wafer container. Substrate: Indium Phosphide wafers, P/E 2"Ø×350±25µm.

 50.8mm InP/InGaAs/InP Epi wafers

Substrate: Indium Phosphide wafers, P/E 2"Ř×380ą25ľm,  n-type P:S[100]ą0.5°,EDP<1E4/cm2.

One-side-polished, back-side matte etched, SEMI Flats.

Epi 1: InGaAs:[100] (100nm, etching stop layer).

Epi 2: InP:[100](50nm, bonding layer).

Wafers for InGaAs Detectors

A scientist prototyping Indium Gallium Arsenide detectors. The research required that a 5 mm diameter InGaAs detector (used at 1590 nm) cost too much.

The scientist asked me to look into alternatives including potentially purchasing a full wafer or more (they expect to need about 350-400 detectors per year) and having someone cut and mount the detectors. I have no idea if this kind of thing is feasible or practical so wanted to start with the simple question of is this kind of approach at all viable? Does your company do things like this (ie. grow the wafers, and have the capability to cut and mount individual detectors)?

UniversityWafer, Inc. quoted the following:

5 mm diameter InGaAs detector (used at 1590 nm), we only offer chips:

Please contact us for pricing.

InGaAs Detector Quote #295539

"Since you used term pixels, we guess you process wafers into arrays from InGaAs structure. According to our experience, extended InGaAs suffer yield issues (pixels with high dark current due to dislocations). This is not a big problem for single eSWIR detectors, but for arrays yield matters much more.

For eSWIR detectors arrays, lattice matched quaternary materials offer comparable performance and more than 99% yield:

Extended InGaAs require thick buffers, which increase the price of epitaxial wafers.

Standard size is 2" wafers, we work on deployment of new reactors, which provide 3" wafers capability soon. We could perhaps grow 1x 3" wafer for tests, but we prefer for now 2".

Pricing depend on structure thickness, and some specs, which might be difficult to meet, eg. background doping or Zinc doping... for example one of  our reactors are not to be used with Zinc (we could grow there InGaAs structures dedicated for planar p-i-n diodes, and 2nd diffusion process), this reactor provide low background doping for standard In0.53GaAs on InP.

Currently, our main effort is bound for research projects on InGaAsSb, therefore we could offer only a limited quantity of commercial wafers of InP/InGaAs ~ 3-6 wafers in each ~2 months. In the future we plan to increase capacity.

Therefore, at that moment of time, we could provide quote for 3x 2" wafers based on your structure. We will not provide a bulk quote.

If you purchase and qualify first wafers, we could discuss further cooperation.

Would you consider InGaAsSb/AlGaAsSb structures as viable alternative options?"

To calculate the cost I do need additional information:

  1. What is required background doping?
  2. Is the diameter 2" O.K?
  3. Is Zinc doping O.K?
  4. What is the thickness of epitaxy layers?
  5. What is XRD Mismatch tolerance?
  6. Type of substrate.
  7. Order size.

Client Replied:

Thank you for the detailed reply. I am aware of the problems arising from the thick buffers of extended InGaAs, but changing materials is a final resort for me right now. I am currently investigating available options for extended InGaAs on InP epitaxial wafers since my group has experience with these materials for processing into arrays. I would like to know the price for extended InGaAs wafers if you are able to grow them. Moreover, any kind of published paper or commercial device connected with extended InGaAs that you have grown is highly desirable.

Below you can see the structure we currently use.
N (#/cm3)
Thickness (nm)
1 E18 
1 E19 
1 E18 
5 E18
1 E19

InP  S.I. SUBSTRATE 300 um
*NID (non-intentionally doped)
Diameter 2" is ok and zinc doping for the p side. I am wondering about your approach of the buffer and cap material choice (InAsP, InAlAs?) and type of buffer (continuously, step graded?). Looking forward to your input.


"The problem is not growth of such structure, problem is whether really this structure will work for you.This is quite strange structure, not what we would expect, and the buffer is so thin!? Perhaps it looks like it was designed, by someone without in depth epitaxy experience.. or it is dedicated to some special narrow use case scenario. Usually in extended SWIR PIN structures, after growth of buffer, all next layers are roughly of same lattice, to not introduce additional strain and dislocations in narrow-bandgap absorber part of device. Usually, it is all InGaAs up to surface, and in your structure there are InP spacers after each InGaAs layer.. which we understand are needed because of etching?

We doubt 85% InGaAs with detector performance (TDD will be very high density, and large dark current, though in 300K difference might be not so bad), could be obtained in practice with such thin InGaAs buffer. Examples of TDD achieved. There will be some Zn diffusion into NID* layer as it is only 100nm, usually grading is done in first P+ layer, by not doping it whole, but first Here some the best references found, and as it could be seen, best results are achieved for more than 2um buffers:

How many iterations of this structure you have done before? We would like to offer you symbolic $200 USD payment for state of the Art SIMS, of your previous sample, to study feasibility - how it was done previously, as we have some doubts, that you could get as "high Indium content (80-85%) InGaAs" in your structure, and it will have satisfying performance. Or please share SIMS if you have for previous iteration. If we found out, that real structure comply with your Layer Table, we could reproduce it.

Do you want repeat, or it is new design, where you would like to go for longer wavelength=higher In content? We have simulated quickly XRD of this structure, to see if there is some pattern from layers structure. Of course InGaAs layer peaks will be clearly visible, and might coincide, and FWHM will be measure of quality, and some insight into composition of all InGaAs layers, and whether they are uniform, and relaxation will be clear as well. Could you share XRD of your earlier samples? I am wondering about your approach of the buffer and cap material choice (InAsP, InAlAs?) and type of buffer (continuously, step graded?). Looking forward to your input." AlInAs buffer also is an option, InAsP would require more cal runs. Why you need cap? it will need to be removed for good contact to InGaAs anyway?"

X value Growth method Substrate TDD in InxGa1-xAs (cm-2) Reference
0.68 MOCVD InP (0 0 1) ~106 (XTEM) Ji et al. [5]
0.82 MOCVD InP (0 0 1) ~108 (XTEM) Zhao et al. [6]
0.82 MOCVD InP (0 0 1) ~1011–1012 (XRD-FWHM) Zhao et al. [7]
0.83 GSMBE InP (0 0 1) ≤107 (XTEM) Present work
0.53 SSMBE GaAs (0 0 1) ~106 (XTEM) Lubyshev et al. [8]
0.6 SSMBE GaAs (0 0 1) ~108 (XTEM) Valtueña et al. [9]
0.75–1 SSMBE GaAs (0 0 1) ~109–1010 (plan-view TEM) Chang et al. [10]
1 SSMBE GaAs (0 0 1) ~108–109 (XTEM) Chang et al. [11]
0.8 Not mentioned GaAs (0 0 1) ~105 (EPD) Zimmermann et al. [12]
0.63 SSMBE GaAs (0 0 1) ~108 (XTEM) Song et al. [13]
0.85 SSMBE GaAs (0 0 1) Not mentioned Jurczak et al. [14]
0.83 GSMBE GaAs (0 0 1) ~109–1010 (XTEM) Present work
0.53 SSMBE Si (1 1 1) Not mentioned Gao et al. [15]

Indium Gallium Arsenide (InGaAs) RC Detector

I may have not been clear. The structure I show is for a lattice matched PIN InGaAs which has been grown here. The thickness of the absorber has been optimised for a resonant cavity enchanced photodetector which we now want to extend to 2.5um. The substrate and up to layer 2 (50nm InP) are indeed getting etched. I am relatively new working with this technology so forgive me for misusing terms such as cap layer which I only wanted to refer to the p+ doped layers 6-8. In the publications you have shared there are always thick absorber layers (1.5-2+ um) and I understand that thin buffers will intoduce defects that degrade the optical properties.  At this point I am aware of different buffer approaches (continiously, step, digital alloy graded) to stop the propagation of TD's. I am looking to understand if you are able to produce a pin with a thin absorber of 100nm with AlInAs buffer and how much would it cost for a single wafer for academic purposes. 

I wanted to correct myself once again since the active InGaAs in the stack I've shared is indeed strained (and not lattice matched as I've thought) and can detect up to 2.2um wavelenghts.

UniversityWafer, Inc. Answered:

Yes, we could assist you in learning the RC detectors. The cost of growth of such a single wafer will be $ USD for a single 2" wafer. You design, we grow, and we conform to layer specs in terms of thickness, molar fraction of InGaAs, AlInAs.

No guarantee on wafers smoothness, crosshatch or if it will work as a detector.

Please provide a complete table with specs, composition of InGaAs, AlInAs you in the epi design, you wish us to grow.
We give you some hints, but it seems you do not yet see the need to discuss the design, and just want to grow something.

We could also assist in epi-design and simulation (Apsys Crosslight), as additional service.